82801BA Datasheet, PDF (357/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

IDE Controller Registers (D31:F1)
10.1.4
10.1.5
10.1.6
STS—Device Status Register (IDE—D31:F1)
Address Offset: 06–07h
Default Value: 0280h
Attribute:
Size:
R/WC, RO
16 bits
Bit
Description
15 Detected Parity Error (DPE)—RO. Reserved as 0.
14 Signaled System Error (SSE)—RO. Reserved as 0.
Received Master-Abort Status (RMA)—R/WC.
13 1 = Bus Master IDE interface function, as a master, generated a master abort.
0 = Cleared by writing a 1 to it.
12 Reserved as 0—RO.
Signaled Target-Abort Status (STA)—R/WC.
11
1 = ICH2 IDE interface function is targeted with a transaction that the ICH2 terminates with a target
abort.
0 = Cleared by writing a 1 to it.
DEVSEL# Timing Status (DEVT)—RO.
10:9 _{01 = Hardwired; however, the ICH2 does not have a real DEVSEL# signal associated with the IDE}
unit, so these bits have no effect.
8 Data Parity Error Detected—RO. Reserved as 0.
7 Fast Back-to-Back Capable—RO. Reserved as 1.
6 User Definable Features (UDF)—RO. Reserved as 0.
5 66 MHz Capable—RO. Reserved as 0.
4:0 Reserved
RID—Revision ID Register (HUB-PCI—D30:F0)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision Identification Number—RO. This 8-bit value indicates the revision number for the ICH2
IDE controller. Refer to the Specification Update for the value of the Revision ID Register.
PI—Programming Interface (IDE—D31:F1)
Address Offset: 09h
Default Value: 80h
Attribute:
Size:
RO
8 bits
Bit
Description
Programming Interface Value—RO.
7:0
80h = The 1b in bit 7 indicates that this IDE controller is capable of bus master operation.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
10-3