82801BA Datasheet, PDF (106/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.7.3
ICW2
The second write in the sequence (ICW2) is programmed to provide bits 7:3 of the interrupt vector
that will be released during an interrupt acknowledge. A different base is selected for each interrupt
controller.
ICW3
The third write in the sequence (ICW3) has a different meaning for each controller.
• For the master controller, ICW3 is used to indicate which IRQ input line is used to cascade the
slave controller. Within the ICH2, IRQ2 is used. Therefore, bit 2 of ICW3 on the master
controller is set to a 1 and the other bits are set to 0s.
• For the slave controller, ICW3 is the slave identification code used during an interrupt
acknowledge cycle. On interrupt acknowledge cycles, the master controller broadcasts a code
to the slave controller if the cascaded interrupt won arbitration on the master controller. The
slave controller compares this identification code to the value stored in its ICW3, and if it
matches, the slave controller assumes responsibility for broadcasting the interrupt vector.
ICW4
The final write in the sequence (ICW4) must be programmed both controllers. At the very least, bit
0 must be set to a 1 to indicate that the controllers are operating in an Intel Architecture-based
system.
Operation Command Words (OCW)
These command words reprogram the Interrupt Controller to operate in various interrupt modes.
• OCW1 masks and unmasks interrupt lines.
• OCW2 controls the rotation of interrupt priorities when in rotating priority mode and controls
the EOI function.
• OCW3 is sets up ISR/IRR reads, enables/disables the Special Mask Mode SMM and enables/
disables polled interrupt mode.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet