82801BA Datasheet, PDF (350/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.10.3
GP_IO_SEL—GPIO Input/Output Select Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +04h
0000FFFFh
No
Attribute:
Size:
Power Well:
R/W
32-bit
Resume
Bit
Description
31:29, 26 15:14,
10:9, 5, 2
28:27,25:24 (ICH2)
28:27,25 (ICH2-M)
24:22, 20:18, 6
(ICH2-M)
23:16 (ICH2)
21:16 (ICH2-M)
13:11, 8:6, 4:3, 1:0
(ICH2)
13:11, 8:7, 4:3, 1:0
(ICH2-M)
Reserved.
GPIO[n] Select (GPIO[n]_SEL)—R/W.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
Reserved
Always 0. The GPIOs are fixed as outputs.
Always 1. These GPIOs are fixed as inputs.
NOTES:
1. There will be some delay on GPIO[24:28] going to their default state based on the rising edge of
RSMRST#. This is the case since these signals are in the resume well and resume well outputs
are not valid until after RSMRST# goes high. ICH2 only guarantees that these GPIOs will be
stable prior to SLP_S3# going active.
9-88
82801BA ICH2 and 82801BAM ICH2-M Datasheet