82801BA Datasheet, PDF (397/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

AC’97 Audio Controller Registers (D31:F5)
13.1.4
13.1.5
13.1.6
PCISTS—PCI Device Status Register (Audio—D31:F5)
Offset:
Default Value
Lockable:
07h–06h
0280h
No
Attribute:
Size:
Power Well:
R/WC
16 bits
Core
PCISTA is a 16-bit status register. Refer to the PCI 2.1 specification for complete details on each
bit.
Bit
Description
15 Detected Parity Error (DPE). Not implemented. Hardwired to 0.
14 SERR# Status (SERRS). Not implemented. Hardwired to 0.
Master-Abort Status (MAS)—R/WC.
13 ^{1 = Bus Master AC '97 2.1 interface function, as a master, generates a master abort.}
0 = Software clears this bit by writing a 1 to the bit position.
12 Reserved. Will always read as 0.
11 Signaled Target-Abort Status (STA). Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEVT)—RO. This 2-bit field reflects the ICH2's DEVSEL# timing when
10:9 ^{performing a positive decode.}
01b = Medium timing.
8
Data Parity Detected (DPD). Not implemented. Hardwired to 0.
7
Fast Back to back Capable (FBC). Hardwired to 1. This bit indicates that the ICH2 as a target is
capable of fast back-to-back transactions.
6
UDF Supported. Not implemented. Hardwired to 0.
5
66 MHz Capable. Hardwired to 0.
4:0 Reserved. Read as 0's.
RID—Revision Identification Register (Audio—D31:F5)
Offset:
Default Value:
Lockable:
08h
See bit description
No
Attribute:
Size:
Power Well:
RO
8 Bits
Core
Bit
Description
7:0
Revision ID Value—RO. Refer to the ICH2 / ICH2-M Specification Update for the value of the
Revision ID Register
PI—Programming Interface Register (Audio—D31:F5)
Offset:
09h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
RO
8 bits
Core
Bit
7:0 Programming Interface—RO.
Description
82801BA ICH2 and 82801BAM ICH2-M Datasheet
13-3