82801BA Datasheet, PDF (140/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.12.5.1
5.12.5.2
Throttling Using STPCLK#
Throttling is used to lower power consumption or reduce heat. The ICH2 asserts STPCLK# to
throttle the processor clock and the processor appears to temporarily enter a C2 state. After a
programmable time, the ICH2 deasserts STPCLK# and the processor appears to return to the C0
state. This allows the processor to operate at reduced average power, with a corresponding decrease
in performance. Two methods are included to start throttling:
• Software enables a timer with a programmable duty cycle. The duty cycle is set by the
THTL_DTY field and the throttling is enabled using the THTL_EN field. This is known as
Manual Throttling. The period is fixed to be in the non-audible range, due to the nature of
switching power supplies.
• A Thermal Override condition (THRM# signal active for >2 seconds) occurs that
unconditionally forces throttling, independent of the THTL_EN bit. The throttling due to
Thermal Override has a separate duty cycle (THRM_DTY) which may vary by field and
system. The Thermal Override condition will end when THRM# goes inactive.
Throttling due to the THRM# signal has higher priority than the software-initiated throttling.
Throttling does not occur when the system is in a C2 state (C2 or C3 for the ICH2-M), even if
Thermal override occurs.
Transition Rules Among S0/Cx and Throttling States
The following priority rules and assumptions apply among the various S0/Cx and throttling states:
• Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This is because
the processor can only perform one register access at a time and Sleep states have higher
priority than thermal throttling.
• When the SLP_EN bit is set (system going to a sleep state (S1–S5), the THTL_EN bit can be
internally treated as being disabled (no throttling while going to sleep state). Note that thermal
throttling (based on THRM# signal) cannot be disabled in an S0 state. However, once the
SLP_EN bit is set, the thermal throttling is shut off (since STPCLK# will be active in S1–S5
states).
• If the THTL_EN bit is set, and a Level 2 (Level 2 or Level 3 for the ICH2-M) read then occurs,
the system should immediately go and stay in a C2 (C2 or C3 for the ICH2-M) state until a
break event occurs. A Level 2 (Level 2 or Level 3 for the ICH2-M) read has higher priority
than the software-initiated throttling or thermal throttling.
• If Thermal Override is causing throttling and a Level 2 (Level 2 or Level 3 for the ICH2-M)
read then occurs, the system will stay in a C2 (C2 or C3 for the ICH2-M) state until a break
event occurs. A Level 2 (Level 2 or Level 3 for the ICH2-M) read has higher priority than the
Thermal Override.
• After an exit from a C2 (C2 or C3 for the ICH2-M) state (due to a Break event), and if the
THTL_EN bit is still set, or if a Thermal Override is still occurring, the system will continue to
throttle STPCLK#. Depending on the time of the break event, the first transition on STPCLK#
active can be delayed by up to one period.
• The Host controller must post Stop-Grant cycles in such a way that the processor gets an
indication of the end of the special cycle prior to the ICH2 observing the Stop-Grant cycle.
This ensures that the STPCLK# signals stays active for a sufficient period after the processor
observes the response phase.
• If in the C1 state and the STPCLK# signal goes active, the processor will generate a Stop-
Grant cycle, and the system should go to the C2 state. When STPCLK# goes inactive, it should
return to the C1 state.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet