82801BA Datasheet, PDF (316/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.8
Power Management Registers (D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0 space, as
well as a separate I/O range. Each register is described below. Unless otherwise indicate, bits are in
the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved
bit, the value should always be 0. Software should not attempt to use the value read from a reserved
bit, as it may not be consistently 1 or 0.
9.8.1 Power Management PCI Configuration Registers (D31:F0)
Table 9-8 shows a small part of the configuration space for PCI Device 31: Function 0. It includes
only those registers dedicated for power management. Some of the registers are only used for
Legacy Power management schemes.
Table 9-8. PCI Configuration Map (PM—D31:F0)
Offset
40h–43h
44h
A0h
A2h
A4h
B8–BBh
C0
C4–CAh
CCh
Mnemonic
ACPI_BASE
ACPI_CNTL
GEN_PMCON_1
GEN_PMCON_2
GEN_PMCON_3
GPI_ROUT
TRP_FWD_EN
MON[n]_TRP_RNG
MON_TRP_MSK
Register Name/Function
ACPI Base Address
ACPI Control
General Power Management Configuration 1
General Power Management Configuration 2
General Power Management Configuration 3
GPI Route Control
I/O Monitor Trap Forwarding Enable
I/O Monitor[4:7] Trap Range
I/O Monitor Trap Range Mask
Default
00000001h
00h
0000h
0000h
00h
00000000h
Type
R/W
R/W
R/W
R/W
R/W
R/W
0000h
0000h
R/W
R/W
9.8.1.1
GEN_PMCON_1—General PM Configuration 1 Register (PM—D31:F0)
Offset Address: A0h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W
16-bit
ACPI, Legacy
Core
Bit
15:12
11
Description
ICH2 (82801BA):
Reserved
ICH2-M (82801BAM):
Global Standby Timer Timeout Count (GST_TIMEOUT) — R/W. For the ICH2-M, this field sets
the number of clock ticks that the Global Standby Timer counts before generating a wake event.
The GST starts counting when the ICH2-M enters the S1 state. If a value of 0h is entered in this
field, the GST does not count and no wake event is generated. The GST_TICK bit sets the tick rate.
ICH2 (82801BA):
Reserved
ICH2-M (82801BAM):
Global Standby Timer Tick Rate (GST_TICK) — R/W.
0 = 1 minute resolution. This yields a GST timeout range of 1 to 15 minutes.
1 = 32 minute resolution, This yields a GST timeout range of 32 minutes to 8 hours.
9-54
82801BA ICH2 and 82801BAM ICH2-M Datasheet