82801BA Datasheet, PDF (202/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Table 5-85. Command Types
Command
Type
Description
0
1
2
3
4
5
6
7–FFh
Reserved
WAKE/SMI#: Wake system if it is not already awake. If the system is already awake, an
SMI# is generated.
Note that the SMB_WAK_STS bit will be set by this command, even if the system is already
awake. The SMI handler should then clear this bit.
Unconditional Powerdown: This command sets the PWRBTNOR_STS bit and has the
same effect as the Powerbutton Override occurring. This functionality depends upon the
BIOS having cleared the PWRBTN_STS bit.
Hard Reset without Cycling: This causes a hard reset of the system (does not include
cycling of the power supply). This is equivalent to a write to the CF9h register with bits 2:1
set to 1, but bit 3 set to 0.
Hard Reset System: This causes a hard reset of the system (including cycling of the power
supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1.
Disable the TCO Messages. This command disables the ICH2 from sending Heartbeat and
Event messages (as described in Section 5.13.2). Once this command has been executed,
Heartbeat and Event message reporting can only be re-enabled by assertion and
deassertion of the RSMRST# signal.
WD RELOAD: Reload watchdog timer.
Reserved
Format of Read Command
The external master performs Byte Read commands to the ICH2 SMBus Slave interface. The
“Command” field (bits 11:18) indicate which register is being accessed. The Data field (bits 30:37)
contain the value that should be read from that register. Table 5-86 shows the Read Cycle format.
Table 5-87 shows the register mapping for the data byte.
Table 5-86. Read Cycle Format
Bit
Description
1 Start
2:8 Slave Address - 7 bits
9 Write
10 ACK
11:18 Command code – 8 bits
19 ACK
20 Repeated Start
21:27 Slave Address - 7 bits
28 Read
29 ACK
30:37 Data Byte
38 NOT ACK
39 Stop
Driven by
Comment
External Microcontroller
External Microcontroller
Must match value in Receive Slave Address
register
External Microcontroller Always 0
ICH2
External Microcontroller
Indicates which register is being accessed.
See Table 5-87.
ICH2
External Microcontroller
External Microcontroller
Must match value in Receive Slave Address
register
External Microcontroller Always 1
ICH2
ICH2
Value depends on register being accessed.
See Table 5-87.
External Microcontroller
ICH2
5-140
82801BA ICH2 and 82801BAM ICH2-M Datasheet