82801BA Datasheet, PDF (261/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.28
8.1.29
PCI_MAST_STS—PCI Master Status Register
(HUB-PCI—D30:F0)
Offset Address: 82h
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
Bit
Description
Internal PCI Master Request Status (INT_MREQ_STS)—R/WC.
7
1 = The ICH2’s internal DMA controller or LPC has requested use of the PCI bus.
0 = Software clears this bit by writing a 1 to the bit position.
Internal LAN Master Request Status (LAN_MREQ_STS)—R/WC.
6
1 = The ICH2’s internal LAN controller has requested use of the PCI bus.
0 = Software clears this bit by writing a 1 to the bit position.
PCI Master Request Status (PCI_MREQ_STS)—R/WC. Allows software to see if a particular bus
master has requested use of the PCI bus. For example, bit 0 will be set if ICH2 has detected
5:0 ^{REQ[0]# asserted and bit 5 will be set if ICH2 detected REQ[5]# asserted.}
1 = The associated PCI master has requested use of the PCI bus.
0 = Software clears these bits by writing a 1 to the bit position.
ERR_CMD—Error Command Register (HUB-PCI—D30:F0)
Offset Address: 90h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
This register configures the ICH2’s Device 30 responses to various system errors. The actual
assertion of the internal SERR# (routed to cause NMI# or SMI#) is enabled via the PCI Command
register.
Bit
Description
7:3 Reserved.
SERR# enable on receiving target abort (SERR_RTA_EN)—R/W.
2
1 = Enable. When SERR_EN is set, the ICH2 will report SERR# when SERR_RTA is set.
0 = Disable
SERR# enable on Delayed Transaction Time-out (SERR_DTT_EN)—R/W.
1
1 = Enable. When SERR_EN is set, the ICH2 will report SERR# when SERR_DTT is set.
0 = Disable.
0 Reserved.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
8-13