82801BA Datasheet, PDF (358/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

IDE Controller Registers (D31:F1)
10.1.7
SCC—Sub Class Code (IDE—D31:F1)
Address Offset: 0Ah
Default Value: 01h
Attribute:
Size:
RO
8 bits
Bit
Description
Sub Class Code—RO.
7:0
01h = IDE device, in the context of a mass storage device.
10.1.8
BCC—Base Class Code (IDE—D31:F1)
Address Offset: 0Bh
Default Value: 01h
Attribute:
Size:
RO
8 bits
Bit
Base Class Code—RO.
7:0
01 = Mass storage device
Description
10.1.9
MLT—Master Latency Timer (IDE—D31:F1)
Address Offset: 0Dh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
Bus Master Latency—RO. The IDE controller is implemented internally, and is not arbitrated as a
7:0 ^{PCI device, so it does not need a Master Latency Timer.}
Hardwired to 00h.
10.1.10
BM_BASE—Bus Master Base Address Register
(IDE—D31:F1)
Address Offset: 20h–23h
Default Value: 00000001h
Attribute:
Size:
R/W
32 bits
The Bus Master IDE interface function uses Base Address register 5 to request a 16 byte IO space
to provide a software interface to the Bus Master functions. Only 12 bytes are actually used
(6 bytes for primary, 6 bytes for secondary). Only bits [15:4] are used to decode the address.
Bit
31:16
15:4
3:1
0
Description
Reserved.
Base Address—R/W. Base address of the I/O space (16 consecutive I/O locations).
Reserved.
Resource Type Indicator (RTE)—RO. Hardwired to 1, indicating a request for IO space.
10-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet