82801BA Datasheet, PDF (387/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

SMBus Controller Registers (D31:F3)
12.1.13 INTR_PN—Interrupt Pin Register (SMBUS—D31:F3)
Address Offset: 3Dh
Default Value: 02h
Attributes:
Size:
RO
8 bits
Bit
Description
Interrupt PIN—RO.
7:0
02h = Indicates that the ICH2 SMBus Controller will drive PIRQB# as its interrupt line.
12.1.14 HOSTC—Host Configuration Register (SMBUS—D31:F3)
Address Offset: 40h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:3 Reserved.
I²C Enable (I2C_EN)—R/W.
2
0 = SMBus behavior.
1 = The ICH2 is enabled to communicate with I²C devices. This will change the formatting of some
commands.
SMBus to SMI Enable (SMB_SMI_EN)—R/W.
0 = SMBus interrupts will not generate an SMI#.
1
1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. This bit will only
take effect if the INTREN bit is set in I/O space.This bit needs to be set for SMBALERT# to be
enabled.
SMBus Host Enable (HST_EN)—R/W.
0 = Disable the SMBus Host Controller.
0
1 = Enable. The SMB Host Controller interface is enabled to execute commands. The INTREN bit
needs to be enabled for the SMB Host Controller to interrupt or SMI#. Note that the SMB Host
Controller will not respond to any new requests until all interrupt requests have been serviced.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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