82801BA Datasheet, PDF (362/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

IDE Controller Registers (D31:F1)
10.1.15
SDMA_CNT—Synchronous DMA Control Register
(IDE—D31:F1)
Address Offset: 48h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:4 Reserved.
Secondary Drive 1 Synchronous DMA Mode Enable (SSDE1)—R/W.
3
0 = Disable (default).
1 = Enable Synchronous DMA mode for secondary channel drive 1
Secondary Drive 0 Synchronous DMA Mode Enable (SSDE0)—R/W.
2
0 = Disable (default).
1 = Enable Synchronous DMA mode for secondary drive 0.
Primary Drive 1 Synchronous DMA Mode Enable (PSDE1)—R/W.
1
0 = Disable (default).
1 = Enable Synchronous DMA mode for primary channel drive 1
Primary Drive 0 Synchronous DMA Mode Enable (PSDE0)—R/W.
0
0 = Disable (default).
1 = Enable Synchronous DMA mode for primary channel drive 0
10.1.16
SDMA_TIM—Synchronous DMA Timing Register
(IDE—D31:F1)
Address Offset: 4A–4Bh
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:14
13:12
11:10
9:8
7:6
Reserved.
Secondary Drive 1 Cycle Time (SCT1)—R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
SCB1 = 0 (33 MHz clk)
SCB1 = 1 (66 MHz clk)
FAST_SCB1 = 1 (133 MHz clk)
00 = CT 4 clocks, RP 6 clocks 00 = Reserved
00 = Reserved
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clks, RP 16 clks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
Reserved.
Secondary Drive 0 Cycle Time (SCT0)—R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
SCB1 = 0 (33 MHz clk)
SCB1 = 1 (66 MHz clk)
FAST_SCB1 = 1 (133 MHz clk)
00 = CT 4 clocks, RP 6 clocks 00 = Reserved
00 = Reserved
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clks, RP 16 clks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
Reserved.
10-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet