82801BA Datasheet, PDF (275/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.1.23
GEN_STS—General Status (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
D4h–D7h
00000F0Xh
No
Attribute:
Size:
Power Well:
R/W
32-bit
Core(0:7), RTC (8:15)
Bit
Description
31:14
13
12
11:8
7:3
2
1
0
Reserved.
TOP_SWAP—R/W.
1 = ICH2 will invert A16 for cycles targeting FWH BIOS space (Does not affect accesses to FWH
feature space).
0 = ICH2 will not invert A16. This bit is cleared by RTCRST# assertion, but not by any other type of
reset.
CPU BIST Enable (CPU_BIST_EN)—R/W. This bit is in the Resume Well and is reset by
RSMRST# (not in the RTC Well and not reset by RTEST#).
1 = The INIT# signal is driven active when CPURST# is active. INIT# goes inactive with the same
timings as the other processor interface signals (Hold Time after CPURST# inactive). Note that
CPURST# is generated by the memory controller hub; however, the ICH2 has a hub interface
special cycle that allows the ICH2 to control the assertion/deassertion of CPURST#.
0 = Disable.
Processor Frequency Strap (FREQ_STRAP[3:0])—R/W. These bits determine the internal
frequency multiplier of the processor. These bits can be reset to 1111 based on an external pin strap
or via the RTCRST# input signal. Software must program this field based on the processor’s
specified frequency. These bits are in the RTC well.
This field is only writeable when SAFE_MODE (bit 2) is cleared to 0. SAFE_MODE is only cleared
by a PWROK rising edge.
Reserved
SAFE_MODE—RO.
1 = ICH2 sampled AC_SDOUT high on the rising edge of PWROK. ICH2 will force
FREQ_STRAP[3:0] bits to all 1s (safe mode multiplier).
0 = ICH2 sampled AC_SDOUT low on the rising edge of PWROK.
NO_REBOOT—R/W (special).
1 = ICH2 will disable the TCO Timer system reboot feature. This bit is set either by hardware when
SPKR is sampled low on the rising edge of PWROK or by software writing a 1 to the bit.
0 = Normal TCO Timer reboot functionality (reboot after 2nd TCO time-out).
Note that this bit cannot be cleared while an external jumper is in place on the SPKR signal.
Reserved.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-13