82801BA Datasheet, PDF (473/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Testability
17.3.1.1
In this example, Vector 1 applies all "0s" to the chain inputs. The outputs being non-inverting, will
consistently produce a "1" at the XOR output on a good board. One short to Vcc (or open floating
to Vcc) will result in a "0" at the chain output, signaling a defect.
Likewise, applying Vector 7 (all "1s") to the chain inputs (given that there are an even number of
input signals in the chain), will consistently produce a "1" at the XOR chain output on a good
board. One short to Vss (or open floating to Vss) will result in a "0" at the chain output, signaling a
defect. It is important to note that the number of inputs pulled to "1" will affect the expected chain
output value. If the number of chain inputs pulled to "1" is even, then expect "1" at the output. If
the number of chain inputs pulled to "1" is odd, expect "0" at the output.
Continuing with the example in Table 17-2, as the input pins are driven to "1" across the chain in
sequence, the XOR Output will toggle between "0" and "1." Any break in the toggling sequence
(e.g., "1011") will identify the location of the short or open.
Test Pattern Consideration for XOR Chain 4
When the ICH2 is operated with the Hub Interface in "Normal" mode (See Section 2.20.1), the
HL_STB and HL_STB# signals must always be driven to complementary logic levels. For
example, if a "1" is driven on HL_STB, then a "0" must be driven on HL_STB# and vice versa.
This will need to be considered in applying test patterns to this chain.
When the ICH2 is operated with the Hub Interface in "Enhanced" mode there are no restrictions on
the values that may be driven onto the HL_STB and HL_STB# signals.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
17-3