82801BA Datasheet, PDF (343/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
Bit
Description
Hub Interface SMI Status (HUBSMI_STS)—R/WC.
1 = ICH2 received an SMI message via the hub interface. The software must read the memory
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controller hub (or its equivalent) to determine the reason for the SMI#.
0 = Software clears this bit by writing a 1 to the bit position.
Hub Interface SCI Status (HUBSCI_STS)—R/WC.
1 = ICH2 received an SCI message via the hub interface. The software must read the memory
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controller hub (or its equivalent) to determine the reason for the SCI.
0 = Software clears this bit by writing a 1 to the bit position.
BIOS Write Status (BIOSWR_STS)—R/WC.
1 = ICH2 sets this bit and generates and SMI# to indicate an illegal attempt to write to the BIOS.
This occurs when either:
a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or
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b) any write is attempted to the BIOS and the BIOSWP bit is also set.
0 = Software clears this bit by writing a 1 to the bit position.
Note:On write cycles attempted to the 4 MB lower alias to the BIOS space, the BIOSWR_STS will
not be set.
New Century Status (NEWCENTURY_STS)—R/WC. This bit is in the RTC well.
1 = This bit is set when the Year byte (RTC I/O space, index offset 09h) rolls over from 99 to 00.
Setting this bit will cause an SMI# (but not a wake event).
0 = Cleared by writing a 1 to the bit position or by RTCRST# going active.
Note that the NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or when
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RTC power has not been maintained). Software can determine if RTC power has not been
maintained by checking the RTC_PWR_STS bit or by other means (e.g., a checksum on RTC
RAM). If RTC power is determined to have not been maintained, BIOS should set the time to a
legal value and then clear the NEWCENTURY_STS bit.
The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared after a “1” is
written to the bit to clear it. After writing a “1” to this bit, software should not exit the SMI handler
until verifying that the bit has actually been cleared. This will ensure that the SMI is not re-entered.
6:4 Reserved
Time Out Status (TIMEOUT)—R/WC.
3
1 = Set by ICH2 to indicate that the SMI was caused by the TCO timer reaching 0.
0 = Software clears this bit by writing a 1 to the bit position.
TCO Interrupt Status (TCO_INT_STS)—R/WC.
2
1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register.
0 = Software clears this bit by writing a 1 to the bit position.
Software TCO SMI Status (SW_TCO_SMI)—R/WC.
1
1 = Software caused an SMI# by writing to the TCO_DAT_IN register.
0 = Software clears this bit by writing a 1 to the bit position.
NMI to SMI Status (NMI2SMI_STS)—RO.
1 = Set by the ICH2 when an SMI# occurs because an event occurred that would otherwise have
0
caused an NMI (because NMI2SMI_EN is set).
0 = Cleared by clearing the associated NMI status bit.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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