82801BA Datasheet, PDF (329/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
Bit
Description
Throttling Enable (THTL_EN). When this bit is set and the system is in a C0 state, processor-
controlled STPCLK# throttling is enabled. The duty cycle is selected in the THTL_DTY field.
4
0 = Disable
1 = Enable
Throttling Duty Cycle (THTL_DTY). This 3-bit field determines the duty cycle of the throttling when
the THTL_EN bit is set. The duty cycle indicates the approximate percentage of time the STPCLK#
signal is asserted (low) while in the throttle mode. The STPCLK# throttle period is 1024 PCICLKs.
THTL_DTY
Throttle Mode
PCI Clocks
000
RESERVED (Default) 512
(Will be 50%)
3:1 ⁰⁰¹
87.5%
896
010
75.0%
768
011
62.5%
640
100
50%
512
101
37.5%
384
110
25%
256
111
12.5%
128
0 Reserved
9.8.3.6
9.8.3.7
LV2—Level 2 Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 14h
(ACPI P_BLK+4)
00h
No
Core
Attribute:
Size:
Usage:
RO
8-bit
ACPI or Legacy
Bit
Description
Reads to this register return all zeros; writes have no effect. Reads to this register generate a “enter
7:0
a level 2 power state” (C2) to the clock control logic. This causes the STPCLK# signal to go active,
and stay active until a break event occurs. Throttling (due either to THTL_EN or THRM# override)
will be ignored.
LV3—Level 3 Register (82801BAM ICH2-M)
I/O Address:
Default Value:
Lockable:
PMBASE + 15h (ACPI P_BLK + 5)
Attribute:
00h
Size:
No
Usage:
Power Well:
RO
8-bit
ACPI or Legacy
Core
Bit
Description
Reads to this register return all zeros, writes to this register have no effect. Reads to this register
7:0 generate an “enter a C3 power state” to the clock control logic. The C3 state persists until a break
event occurs.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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