82801BA Datasheet, PDF (413/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

AC’97 Modem Controller Registers (D31:F6)
14.1.4
14.1.5
14.1.6
PCISTA—Device Status Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
07h–06h
0280h
No
Attribute:
Size:
Power Well:
R/WC
16 bits
Core
PCISTA is a 16-bit status register. Refer to the PCI 2.1 specification for complete details on each
bit.
Bit
Description
15 Detected Parity Error (DPE)—RO. Not implemented. Hardwired to 0.
14 SERR# Status (SERRS)—RO. Not implemented. Hardwired to 0.
Master-Abort Status (MAS)—R/WC.
13 ^{1 = Bus Master AC ‘97 interface function, as a master, generates a master abort.}
0 = Software clears this bit by writing a 1 to the bit position.
12 Reserved. Read as “0”.
11 Signaled Target-Abort Status (STA)—RO. Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEVT)—RO. This 2-bit field reflects the ICH2's DEVSEL# timing
10:9 parameter. These read only bits indicate the ICH2's DEVSEL# timing when performing a positive
decode.
8 Data Parity Detected (DPD)—RO. Not implemented. Hardwired to 0.
7
Fast Back to back Capable (FBC)—RO. Hardwired to 1. This bit indicates that the ICH2 as a target is
capable of fast back-to-back transactions.
6 UDF Supported—RO. Not implemented. Hardwired to 0.
5 66 MHz Capable—RO. Hardwired to 0.
4:0 Reserved. Read as 0s.
RID—Revision Identification Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
08h
See bit description
No
Attribute:
Size:
Power Well:
RO
8 Bits
Core
Bit
Description
7:0
Revision ID Value—RO. Refer to the Specification Update for the value of the Revision ID
Register
PI—Programming Interface Register (Modem—D31:F6)
Address Offset: 09h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
RO
8 bits
Core
Bit
Description
7:0
Programming Interface Value—RO.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
14-3