82801BA Datasheet, PDF (130/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.11.1.5
5.11.1.6
STPCLK# and CPUSLP# Signals
The ICH2 power management logic controls these active-low signals. Refer to Section 5.12 for
more information on the functionality of these signals.
CPUPWRGOOD Signal
This signal is connected to the processor’s PWRGOOD input. This is an open-drain output signal
(external pull-up resistor required) that represents a logical AND of the ICH2’s PWROK and
VRMPWRGD (VGATE/VRMPWRGD for ICH2-M) signals.
82801BAM ICH2-M: For Intel^® SpeedStep^TM technology support, this signal is kept high during
a Intel^® SpeedStep^TM state transition to prevent loss of processor context.
5.11.2 Dual Processor Issues (82801BA ICH2 only)
5.11.2.1
Signal Differences (82801BA ICH2 only)
In dual-processor designs, some of the processor signals are unused or used differently than for
uniprocessor designs.
Table 5-33. DP Signal Differences (82801BA ICH2 only)
Signal
A20M# / A20GATE
STPCLK#
FERR# / IGNNE#
Difference
Generally not used, but still supported by the 82801BA ICH2.
Used for S1 State as well as preparation for entry to S3–S5
Also allows for THERM# based throttling (not via ACPI control methods).
Should be connected to both processors.
Generally not used, but still supported by 82801BA ICH2.
5.11.2.2 Power Management (82801BA ICH2 only)
For the 82801BA ICH2, attempting clock control with more than one processor is not feasible.
This is because the host controller does not provide any indication as to which processor is
executing a particular Stop-Grant cycle. Without this information, there is no way for the ICH2 to
know when it is safe to deassert STPCLK#.
Because the S1 state has the STPCLK# signal active, the STPCLK# signal can be connected to
both processors. However, for ACPI implementations, the ICH2 does not support the C2 state for
both processors, since there are not two processor control blocks. BIOS must indicate that the
ICH2 only supports the C1 state for dual-processor designs. However, the THRM# signal can be
used for overheat conditions to activate thermal throttling.
When entering S1, the ICH2 asserts STPCLK# to both processors. To meet the processor
specifications, the CPUSLP# signal has to be delayed until the 2^nd Stop-Grant cycle occurs. To
ensure this, the ICH2 waits a minimum or 60 PCI clocks after receipt of the first Stop-Grant cycle
before asserting CPUSLP# (if the SLP_EN bit is set to 1).
5-68
82801BA ICH2 and 82801BAM ICH2-M Datasheet