82801BA Datasheet, PDF (359/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

IDE Controller Registers (D31:F1)
10.1.11
IDE_SVID—Subsystem Vendor ID (IDE—D31:F1)
Address Offset:
Default Value:
Lockable:
2Ch–2Dh
00h
No
Attribute:
Size:
Power Well:
R/Write-Once
16 bits
Core
Bit
Description
Subsystem Vendor ID (SVID)—R/Write-Once. The SVID register, in combination with the
Subsystem ID (SID) register, enables the operating system (OS) to distinguish subsystems from
15:0 each other. Software (BIOS) sets the value in this register. After that, the value can be read, but
subsequent writes to this register have no effect. The value written to this register will also be
readable via the corresponding SVID registers for the USB#1, USB#2 and SMBus functions.
10.1.12
IDE_SID—Subsystem ID (IDE—D31:F1)
Address Offset:
Default Value:
Lockable:
2Eh–2Fh
00h
No
Attribute:
Size:
Power Well:
R/Write-Once
16 bits
Core
Bit
Description
Subsystem ID (SID)—R/Write-Once. The SID register, in combination with the SVID register,
enables the operating system (OS) to distinguish subsystems from each other. Software (BIOS)
15:0 sets the value in this register. After that, the value can be read, but subsequent writes to this register
have no effect. The value written to this register will also be readable via the corresponding SID
registers for the USB#1, USB#2 and SMBus functions.
10.1.13
IDE_TIM—IDE Timing Register (IDE—D31:F1)
Address Offset:
Default Value:
Primary: 40–41h
Secondary: 42–43h
0000h
Attribute:
Size:
R/W
16 bits
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA transfers. It
also controls operation of the buffer for PIO transfers.
Bit
15
14
13:12
Description
IDE Decode Enable (IDE)—R/W. Individually enable/disable the Primary or Secondary decode.
The IDE I/O Space Enable bit in the Command register must be set in order for this bit to have any
effect. Additionally, separate configuration bits are provided (in the IDE I/O Configuration register)
to individually disable the primary or secondary IDE interface signals, even if the IDE Decode
Enable bit is set.
0 = Disable.
1 = Enables the ICH2 to decode the associated Command Blocks (1F0h–1F7h for primary,
170h–177h for secondary) and Control Block (3F6h for primary and 376h for secondary).
Drive 1 Timing Register Enable (SITRE)—R/W.
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1
IORDY Sample Point (ISP). The setting of these bits determine the number of PCI clocks between
IDE IOR#/IOW# assertion and the first IORDY sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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