82801BA Datasheet, PDF (87/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.3.1.9
I/O Cycles
For I/O cycles targeting registers specified in the ICH2’s decode ranges, the ICH2 performs I/O
cycles as defined in the LPC specification. These are 8-bit transfers. If the processor attempts a
16-bit or 32-bit transfer, the ICH2 will break the cycle up into multiple 8-bit transfers to
consecutive I/O addresses.
Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH2 returns all
1s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up
resistors would keep the bus high if no device responds.
5.3.1.10
Bus Master Cycles
The ICH2 supports Bus Master cycles and requests (using LDRQ#) as defined in the LPC
specification. The ICH2 has two LDRQ# inputs; thus, ICH2 supports two separate bus master
devices. It uses the associated START fields for Bus Master 0 (‘0010b’) or Bus Master 1 (‘0011b’).
Note: The ICH2 does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters should only
perform memory read or memory write cycles.
5.3.1.11 LPC Power Management
LPCPD# Protocol
Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals will drive
LDRQ# low or tri-state it. ICH2 shuts off the LDRQ# input buffers. After driving SUS_STAT#
active, the ICH2 drives LFRAME# low and tri-states (or drive low) LAD[3:0].
CLKRUN# Protocol (82801BAM ICH2-M only)
For the ICH2-M, the CLKRUN# protocol is the same as the PCI specification. Stopping the PCI
clock stops the LPC clock.
5.3.1.12 Configuration and ICH2 Implications
LPC Interface Decoders
To allow the I/O cycles and memory mapped cycles to go to the LPC I/F, the ICH2 includes several
decoders. During configuration, the ICH2 must be programmed with the same decode ranges as the
peripheral. The decoders are programmed via the Device 31:Function 0 configuration space.
Note:
The ICH2 can not accept PCI write cycles from PCI-to-PCI bridges or devices with similar
characteristics (specifically those with a “Retry Read” feature which is enabled) to an LPC device
if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are
not part of normal system operation; however, they may be encountered as part of platform
validation testing using custom test fixtures.
Bus Master Device Mapping and START Fields
Bus Masters must have a unique START field. In the case of the ICH2, which supports 2 LPC bus
masters, it will drive 0010 for the START field for grants to bus master #0 (requested via
LDRQ[0]#) and 0011 for grants to bus master #1 (requested via LDRQ[1]#.). Thus, no registers are
needed to configure the START fields for a particular bus master.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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