82801BA Datasheet, PDF (122/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.9
5.9.1
5.9.2
Serial Interrupt (D31:F0)
ICH2 supports a serial IRQ scheme. This allows a single signal to be used to report interrupt
requests. The signal (used to transmit this information) is shared between the host, the ICH2, and
all peripherals that support serial interrupts. The signal line (SERIRQ) is synchronous to PCI clock
and follows the sustained tri-state protocol that is used by all PCI signals. This means that if a
device has driven SERIRQ low, it will first drive it high synchronous to PCI clock and release it the
following PCI clock. The serial IRQ protocol defines this sustained tri-state signaling in the
following fashion:
• S - Sample Phase. Signal driven low
• R - Recovery Phase. Signal driven high
• T - Turn-around Phase. Signal released
The ICH2 supports a message for 21 serial interrupts. These represent the 15 ISA interrupts
(IRQ[0,1, 2:15]), the four PCI interrupts, and the SMI# and IOCHK# control signals. The serial
IRQ protocol does not support the additional APIC interrupts (20–23).
Start Frame
The serial IRQ protocol has two modes of operation which affect the start frame. These two modes
are:
• Continuous, where the ICH2 is solely responsible for generating the start frame
• Quiet, where a serial IRQ peripheral is responsible for beginning the start frame.
The mode that must first be entered when enabling the serial IRQ protocol is continuous mode. In
this mode, the ICH2 will assert the start frame. This start frame is 4, 6, or 8 PCI clocks wide based
upon the Serial IRQ Control Register, bits 1:0 at 64h in Device 31:Function 0 configuration space.
This is a polling mode.
When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the SERIRQ line
remains inactive and pulled up between the Stop and Start Frame until a peripheral drives the
SERIRQ signal low. The ICH2 senses the line low and continues to drive it low for the remainder
of the Start Frame. Since the first PCI clock of the start frame was driven by the peripheral in this
mode, the ICH2 drives the SERIRQ line low for 1 PCI clock less than in continuous mode. This
mode of operation allows for a quiet and, therefore, lower power operation.
Data Frames
Once the Start frame has been initiated, all of the SERIRQ peripherals must start counting frames
based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly 3 phases of
1 clock each:
• Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the
corresponding interrupt signal is low. If the corresponding interrupt is high, the SERIRQ
devices tri-state the SERIRQ signal. The SERIRQ line remains high due to pull-up resistors. A
low level during the IRQ0-1 and IRQ2-15 frames indicates that an active-high ISA interrupt is
not being requested, but a low level during the PCI INT[A:D], SMI#, and IOCHK# frame
indicates that an active-low interrupt is being requested.
• Recovery Phase. During this phase, the device drives the SERIRQ line high if in the Sample
Phase it was driven low. If it was not driven in the sample phase, it is tri-stated in this phase.
• Turn-around Phase. The device will tri-state the SERIRQ line.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet