82801BA Datasheet, PDF (273/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.1.21
9.1.22
PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
90h–91h
0000h
No
Attribute:
Size:
Power Well:
R/W
16-bit
Core
Bit
Description
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Channel 7 Select—R/W.
00 = Reserved
01 = PC/PCI DMA
10 = Reserved
11 = LPC I/F DMA
Channel 6 Select—R/W. Same bit decode as for Channel 7
Channel 5 Select—R/W. Same bit decode as for Channel 7
Reserved.
Channel 3 Select—R/W. Same bit decode as for Channel 7
Channel 2 Select—R/W. Same bit decode as for Channel 7
Channel 1 Select—R/W. Same bit decode as for Channel 7
Channel 0 Select—R/W. Same bit decode as for Channel 7
GEN_CNTL—General Control Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
D0h–D3h
00000000h
No
Attribute:
Size:
Power Well:
R/W
32-bit
Core
Bit
Description
31:26
25
24
23:14
13
12
Reserved.
REQ[5]#/GNT[5]# PC/PCI protocol select (PCPCIB_SEL)—R/W.
1 = When this bit is set to a 1, the PCI REQ[5]#/GNT[5]# signal pair will use the PC/PCI protocol as
REQ[B]#/GNT[B]. The corresponding bits in the GPIO_USE_SEL register must also be set to a
0. If the corresponding bits in the GPIO_USE_SEL register are set to a 1, the signals will be
used as a GPI and GPO.
0 = The REQ[5]#/GNT[5]# pins will function as a standard PCI REQ/GNT signal pair.
Hide ISA Bridge (HIDE_ISA)—R/W.
1 = Software sets this bit to 1 to disable configuration cycle from being claimed by a PCI-to-ISA
bridge. This prevents the operating system PCI PnP from getting confused by seeing two ISA
bridges. It is required for the ICH2 PCI address line AD22 to connect to the PCI-to-ISA bridge’s
IDSEL input. When this bit is 1, the ICH2 does not assert AD22 during configuration cycles to
the PCI-to-ISA bridge.
0 = The ICH2 does not prevent AD22 from asserting during configuration cycles to the PCI-to-ISA
bridge.
Reserved.
Coprocessor Error Enable (COPR_ERR_EN)—R/W.
1 = When FERR# is low, ICH2 generates IRQ13 internally and holds it until an I/O write to port F0h.
It will also drive IGNNE# active.
0 = FERR# will not generate IRQ13 nor IGNNE#.
Keyboard IRQ1 Latch Enable (IRQ1LEN)—R/W.
1 = The active edge of IRQ1 will be latched and held until a port 60h read.
0 = IRQ1 will bypass the latch.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-11