82801BA Datasheet, PDF (203/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Table 5-87. Data Values for Slave Read Registers
Register Bits
Description
0
1
1
2
2
3
3
4
4
4
4
4
4
5
5
6
7
8
9–FFh
7:0 Reserved.
System Power State
2:0 000 = S0 001 = S1 010 = Reserved 011 = S3
100 = S4 101 = S5 110 = Reserved 111 = Reserved
7:3 Reserved
3:0 Frequency Strap Register
7:4 Reserved
5:0 Watchdog Timer current value
7:6 Reserved
0
1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has
probably been opened.
1
1 = BTI Temperature Event occurred. This bit is set if the ICH2’s THRM# input signal is
active. Need to take after polarity control.
2 DOA processor status. This bit is 1 to indicate that the processor is dead.
3 1 = Watchdog timer expired. This bit is set if the ICH2’s TCO timers have timed out.
6:4 Reserved.
7 Will reflect the state of the ICH2’s GPIO[11].
0
Unprogrammed FWH bit. This bit will be 1 to indicate that the first BIOS fetch returned
FFh, which indicates that the FWH is probably blank.
7:1 Reserved
7:0 Contents of the Message 1 register. See Section 9.9.10.
7:0 Contents of the Message 2 register. See Section 9.9.10.
7:0 Contents of the WDSTATUS register. See Section 9.9.11.
7:0 Reserved
Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a
Start bit - Address - Write bit sequence. When the ICH2 detects that the address matches the value
in the Receive Slave Address register, it assumes that the protocol is always followed and ignores
the Write bit (bit 9) and signal an Acknowledge during bit 10 (See Table 5-83 and Table 5-86). In
other words, if a Start - Address - Read occurs (which is illegal for SMBus Read or Write protocol),
and the address matches the ICH2’s Slave Address, the ICH2 will still grab the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start - Address - Read
sequence beginning at bit 20 (See Table 5-86). Once again, if the Address matches the ICH2’s
Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and proceed with
the Slave Read cycle.
Note: An external microcontroller must not attempt to access the ICH2’s SMBus Slave logic until at least
1 second after both RTCRST# and RSMRST# are deasserted (high).
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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