82801BA Datasheet, PDF (38/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Signal Description
2.3
EEPROM Interface
Table 2-3. EEPROM Interface Signals
Name
EE_SHCLK
EE_DIN
EE_DOUT
EE_CS
Type
Description
O EEPROM Shift Clock: EE_SHCLK is the serial shift clock output to the EEPROM.
I
EEPROM Data In: EE_DIN transfers data from the EEPROM to the ICH2. This
signal has an integrated pull-up resistor.
O EEPROM Data Out: EE_DOUT transfers data from the ICH2 to the EEPROM.
O EEPROM Chip Select: EE_CS is a chip-select signal to the EEPROM.
2.4
Firmware Hub Interface
Table 2-4. Firmware Hub Interface Signals
Name
FWH[3:0] /
LAD[3:0]
FWH[4] /
LFRAME#
Type
Description
I/O Firmware Hub Signals: These signals are muxed with LPC address signals.
I/O Firmware Hub Signals: This signal is muxed with LPC LFRAME# signal.
2.5
PCI Interface
Table 2-5. PCI Interface Signals
Name
AD[31:0]
C/BE[3:0]#
Type
Description
PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first
I/O
clock of a transaction, AD[31:0] contain a physical address (32 bits). During
subsequent clocks, AD[31:0] contain data. The ICH2 drives all 0s on AD[31:0]
during the address phase of all PCI Special Cycles.
Bus Command and Byte Enables: The command and byte enable signals are
multiplexed on the same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the
Byte Enables.
C/BE[3:0]# Command Type
0000
0001
0010
0011
I/O
0110
0111
1010
1011
1100
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate
All command encodings not shown are reserved. The ICH2 does not decode
reserved values, and therefore will not respond if a PCI master generates a cycle
using one of the reserved values.
2-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet