82801BA Datasheet, PDF (24/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

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Short Message............................................................................................5-52
APIC Bus Status Cycle Definition ...............................................................5-53
Lowest Priority Message (Without Focus Processor) .................................5-54
Remote Read Message ..............................................................................5-55
Interrupt Message Address Format ............................................................5-58
Interrupt Message Data Format..................................................................5-59
Stop Frame Explanation .............................................................................5-61
Data Frame Format ....................................................................................5-62
Configuration Bits Reset By RTCRST# Assertion ......................................5-65
INIT# Going Active......................................................................................5-67
NMI Sources ...............................................................................................5-67
DP Signal Differences (82801BA ICH2 only)..............................................5-68
Frequency Strap Behavior Based on Exit State .........................................5-69
Frequency Strap Bit Mapping .....................................................................5-69
General Power States for Systems using ICH2..........................................5-72
State Transition Rules for ICH2 ..................................................................5-73
System Power Plane ..................................................................................5-74
Causes of SMI# and SCI ............................................................................5-75
Break Events ..............................................................................................5-77
Sleep Types................................................................................................5-81
Causes of Wake Events .............................................................................5-82
GPI Wake Events .......................................................................................5-82
Sleep State Exit Latencies..........................................................................5-83
Transitions Due To Power Failure ..............................................................5-83
Transitions Due to Power Button ................................................................5-87
Transitions Due to RI# signal......................................................................5-88
Write Only Registers with Read Paths in Alternate Access Mode..............5-89
PIC Reserved Bits Return Values...............................................................5-91
Register Write Accesses in Alternate Access Mode...................................5-91
ICH2 Clock Inputs.......................................................................................5-93
Alert on LAN* Message Data......................................................................5-97
IDE Transaction Timings (PCI Clocks) .....................................................5-100
Interrupt/Active Bit Interaction Definition...................................................5-103
UltraATA/33 Control Signal Redefinitions.................................................5-105
Frame List Pointer Bit Description ............................................................5-108
TD Link Pointer .........................................................................................5-109
TD Control and Status ..............................................................................5-110
TD Token ..................................................................................................5-112
TD Buffer Pointer ......................................................................................5-112
Queue Head Block....................................................................................5-113
Queue Head Link Pointer .........................................................................5-113
Queue Element Link Pointer.....................................................................5-113
Command Register, Status Register and TD Status Bit Interaction .........5-115
Queue Advance Criteria ...........................................................................5-117
USB Schedule List Traversal Decision Table ...........................................5-118
PID Format ...............................................................................................5-120
PID Types .................................................................................................5-121
Address Field............................................................................................5-121
Endpoint Field...........................................................................................5-122
Token Format ...........................................................................................5-123
SOF Packet ..............................................................................................5-123
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82801BA ICH2 and 82801BAM ICH2-M Datasheet