82801BA Datasheet, PDF (42/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Signal Description
2.7
LPC Interface
Table 2-7. LPC Interface Signals
Name
Type
Description
LAD[3:0] /
FWH[3:0]
I/O LPC Multiplexed Command, Address, Data: Internal pull-ups are provided.
LFRAME# /
FWH[4]
O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.
LPC Serial DMA/Master Request Inputs: These signals are used to request DMA or
LDRQ[1:0]# I bus master access. Typically, they are connected to external Super I/O device. An
internal pull-up resistor is provided on these signals.
2.8
Interrupt Interface
Table 2-8. Interrupt Signals
Name
SERIRQ
PIRQ[D:A]#
PIRQ[H]#,
PIRQ[G:F]# /
GPIO[4:3],
PIRQ[E]#
IRQ[14:15]
APICCLK
APICD[1:0]
Type
I/O
I/OD
I/OD
I
I
I/OD
Description
Serial Interrupt Request: This pin implements the serial interrupt protocol.
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to
interrupts 3:7, 9:12, 14, or 15 as described in the Interrupt Steering section. Each
PIRQx# line has a separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC in the following
fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18,
and PIRQ[D]# to IRQ19. This frees the ISA interrupts.
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to
interrupts 3:7, 9:12, 14 or 15 as described in the Interrupt Steering section. Each
PIRQx# line has a separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC in the following
fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22,
and PIRQ[H]# to IRQ23. This frees the ISA interrupts. If not needed for interrupts,
PIRQ[G:F] can be used as GPIO.
Interrupt Request 14:15: These interrupt inputs are connected to the IDE drives.
IRQ14 is used by the drives connected to the primary controller and IRQ15 is used
by the drives connected to the secondary controller.
APIC Clock: The APIC clock runs at 33.333 MHz.
APIC Data: These bi-directional open drain signals are used to send and receive
data over the APIC bus. As inputs, the data is valid on the rising edge of APICCLK.
As outputs, new data is driven from the rising edge of the APICCLK.
2-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet