82801BA Datasheet, PDF (344/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.9.7
TCO2_STS—TCO2 Status Register
I/O Address:
Default Value:
Lockable:
TCOBASE +06h
0000h
No
Attribute:
Size:
Power Well:
R/WC, RO
16-bit
Resume
(Except Bit 0, in RTC)
Bit
Description
15:3
2
1
0
Reserved
Boot Status (BOOT_STS):
1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not fetched the
first instruction.
0 = Cleared by ICH2 based on RSMRST# or by software writing a 1 to this bit. Note that software
should first clear the SECOND_TO_STS bit before writing a 1 to clear the BOOT_STS bit.
If rebooting due to a second TCO timer time-out and if the BOOT_STS bit is set, the ICH2 will reboot
using the ‘safe’ multiplier (1111). This allows the system to recover from a processor frequency
multiplier that is too high, and allows the BIOS to check the BOOT_STS bit at boot. If the bit is set and
the frequency multiplier is 1111, then the BIOS knows that the processor has been programmed to an
illegal multiplier.
Second TCO Time-out Status (SECOND_TO_STS)—R/WC.
1 = The ICH2 sets this bit to a 1 to indicate that the TCO timer timed out a second time (probably due
to system lock). If this bit is set the ICH2 will reboot the system after the second time-out. The
reboot is done by asserting PCIRST#.
0 = This bit is cleared by writing a 1 to the bit position or by a RSMRST#.
Intruder Detect (INTRD_DET)—R/WC.
1 = Set by ICH2 to indicate that an intrusion was detected. This bit is set even if the system is in G3
state.
0 = This bit is only cleared by writing a 1 to the bit position, or by RTCRST# assertion.
9-82
82801BA ICH2 and 82801BAM ICH2-M Datasheet