82801BA Datasheet, PDF (21/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

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Required External RTC Circuit....................................................................2-16
Example V5REF Sequencing Circuit ..........................................................2-16
ICH2 and System Clock Domains................................................................4-1
Conceptual System Clock Diagram (82801BA ICH2 and
82801BAM ICH2-M)......................................................................................4-2
Primary Device Status Register Error Reporting Logic.................................5-3
Secondary Status Register Error Reporting Logic ........................................5-3
NMI# Generation Logic .................................................................................5-4
Integrated LAN Controller Block Diagram.....................................................5-7
64-Word EEPROM Read Instruction Waveform .........................................5-17
LPC Interface Diagram ...............................................................................5-21
Typical Timing for LFRAME# ......................................................................5-24
Abort Mechanism ........................................................................................5-24
ICH2 DMA Controller ..................................................................................5-26
DMA Serial Channel Passing Protocol .......................................................5-30
DMA Request Assertion Through LDRQ# ..................................................5-34
Coprocessor Error Timing Diagram ............................................................5-67
Signal Strapping..........................................................................................5-70
Intel^® SpeedStep™ Block Diagram (82801BAM ICH2-M only) ..................5-85
Physical Region Descriptor Table Entry ...................................................5-101
Transfer Descriptor ...................................................................................5-109
Example Queue Conditions ......................................................................5-116
USB Data Encoding ..................................................................................5-119
USB Legacy Keyboard Flow Diagram ......................................................5-128
ICH2 Based AC’97 2.1..............................................................................5-143
AC’97 2.1 Controller-Codec Connection...................................................5-144
AC-link Protocol ........................................................................................5-145
AC-link Powerdown Timing.......................................................................5-151
SDIN Wake Signaling ...............................................................................5-152
FWH Memory Cycle Preamble .................................................................5-155
Single Byte Read ......................................................................................5-155
Single Byte Write ......................................................................................5-156
ICH2 82801BA and ICH2-M 82801BAM Ballout
(Top view — Left side) ................................................................................15-2
ICH2 82801BA and ICH2-M 82801BAM Ballout
(Top view — Right side)..............................................................................15-3
ICH2 / ICH2-M Package (Top and Side Views) ........................................15-14
ICH2 / ICH2-M Package (Bottom View)....................................................15-15
Clock Timing .............................................................................................16-18
Valid Delay From Rising Clock Edge ........................................................16-18
Setup And Hold Times ..............................................................................16-18
Float Delay................................................................................................16-18
Pulse Width...............................................................................................16-19
Output Enable Delay.................................................................................16-19
IDE PIO Mode...........................................................................................16-19
IDE Multiword DMA...................................................................................16-20
Ultra ATA Mode (Drive Initiating a Burst Read) ........................................16-20
Ultra ATA Mode (Sustained Burst)............................................................16-21
Ultra ATA Mode (Pausing a DMA Burst)...................................................16-21
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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