82801BA Datasheet, PDF (196/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Block Read/Write
The Block Write begins with a slave address and a write condition. After the command code, the
ICH2 issues a byte count which describes how many more bytes will follow in the message. If a
slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of
data. The byte count may not be 0.
Note that, unlike the PIIX4, which implements 32-byte buffer for Block Read/Write command, the
ICH2 implements the Block Data Byte register (D31:F3, I/O offset 07h) for Block Read/Write
command.
When programmed for a block write command, the Transmit Slave Address, Host Command, and
Data0 (count) registers are sent. Data is then sent from the Block Data Byte register. After the byte
has been sent, the ICH2 sets the BYTE_DONE_STS bit in the Host Status register. If there are
more bytes to send, software writes the next byte to the Block Data Byte register and also clears the
BYTE_DONE_STS bit. The ICH2 then sends the next byte. When doing a block write, first poll
the BYTE_DONE_STS register until it is set, then write the next byte, then clear the
BYTE_DONE_STS register.
On block read commands, after the byte count is stored in the DATA 0 register, the first data byte
goes in the Block Data Byte Register; the ICH2 will then set the BYTE_DONE_STS bit and
generate an SMI# or interrupt. The SMI# or interrupt handler reads the byte and then clears the
BYTE_DONE_STS bit to allow the next byte to be read into the Block Data Byte register. Note
that after receiving data byte N-1 of the block, the software needs to set the LAST_BYTE bit in the
Host Control Register; this allows the ICH2 to send a NOT ACK (instead of an ACK) after
receiving the last data byte (byte N) of the block.
After each byte of a block message the ICH2 sets the BYTE_DONE_STS bit and generates an
interrupt or SMI#. Software clears the BYTE_DONE_STS bit before the next transfer occurs.
When the interrupt handler clears the BYTE_DONE_STS bit after the last byte has been
transferred, the ICH2 sets the INTR bit and generates another interrupt to signal the end of the
block transfer. Thus, for a block message of n bytes, the ICH2 generates n+1 interrupts. The
interrupt handler needs to be implemented to handle all of these interrupts
The format of the Block Read/Write protocol is shown in Table 5-81.
Note: For Block Write, if the I²C_EN bit is set, the format of the command changes slightly. The ICH2
still sends the number of bytes indicated in the DATA0 register. However, it does not send the
contents of the Data 0 register as part of the message.
5-134
82801BA ICH2 and 82801BAM ICH2-M Datasheet