82801BA Datasheet, PDF (116/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Lowest Priority without Focus Processor (FP) Message
This message format is used to deliver an interrupt in the lowest priority mode in which it does not
have a Focus Process. Cycles 1 through 21 for this message are same as for the short message
discussed above. Status cycle 19 identifies if there is a Focus processor (10) and a status value of
11 in cycle 20 indicates the need for lowest priority arbitration.
Table 5-24. Lowest Priority Message (Without Focus Processor)
Cycle
Bit 1
Bit 0
Comments
1
1
0
Normal Arbitration
2–5
ARBID
1
Arbitration ID
6
NOT(DM)
NOT(M2) DM = Destination Mode from bit 11 of the redirection table register
7
NOT(M1)
NOT(M0)
M2-M0 = Delivery Mode from bits 10:8 of the redirection table
register
8
NOT(L)
NOT(TM) L = Level, TM = Trigger Mode
9
NOT(V7)
NOT(V6)
10
NOT(V5)
NOT(V4)
Interrupt vector bits V7–V0 from redirection table register
11
NOT(V3)
NOT(V2)
12
NOT(V1)
NOT(V0)
13
NOT(D7)
NOT(D6)
14
NOT(D5)
NOT(D4)
Destination field from bits 63:56 of redirection table register
15
NOT(D3)
NOT(D2)
16
NOT(D1)
NOT(D0)
17
NOT(C1)
NOT(C0) Checksum for Cycles 6–16
18
1
1
Postamble
19
NOT(A)
NOT(A) Status Cycle 0.
20
NOT(A1)
NOT(A1) Status Cycle 1.
21
P7
1
22
P6
1
23
P5
1
24
P4
25
P3
1
Inverted Processor Priority P7–P0
1
26
P2
1
27
P1
1
28
P0
1
29
ArbID3
1
30
ArbID2
1
31
ArbID1
1
32
ArbID0
1
33
S
S
Status
34
1
1
Idle
NOTES:
1. Cycle 21 through 28 are used to arbitrate for the lowest priority processor. The processor that takes part in
the arbitration drives the processor priority on the bus. Only the local APICs that have "free interrupt slots" will
participate in the lowest priority arbitration.
2. Cycles 29 through 32 are used to break tie in case two more processors have lowest priority. The bus
arbitration IDs are used to break the tie.
5-54
82801BA ICH2 and 82801BAM ICH2-M Datasheet