82801BA Datasheet, PDF (318/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.8.1.2
GEN_PMCON_2—General PM Configuration 2 Register (PM—D31:F0)
Offset Address: A2h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/WC
16-bit
ACPI, Legacy
Resume
Bit
Description
7:2 Reserved.
CPU Power Failure (CPUPWR_FLR)—R/WC.
0 = Software clears this bit by writing a 1 to the bit position..
ICH2 (82801BA):
1 1 = Indicates that the VRMPWRGD signal from the processor’s VRM went low.
ICH2-M (82801BAM):
1 = Indicates that the VGATE signal from the processor’s VRM went low. This bit will not be set if
VGATE went low due to a Intel^® SpeedStep^™ transition.
PWROK Failure (PWROK_FLR)—R/WC.
0 = Software clears this bit by writing a 1 to the bit position, or when the system goes into a G3
state.
1 = This bit will be set any time PWROK goes low, when the system was in S0 or S1 state. The bit
will be cleared only by software by writing a 1 to this bit or when the system goes to a G3 state.
0 ^{Note: Traditional designs have a reset button logically ANDed with the PWROK signal from the}
power supply and the processor’s voltage regulator module. If this is done with the ICH2, the
PWROK_FLR bit will be set. The ICH2 treats this internally as if the RSMRST# signal had
gone active. However, it is not treated as a full power failure. If PWROK goes inactive and
then active (but RSMRST# stays high), then the ICH2 will reboot (regardless of the state of
the AFTERG3 bit). If the RSMRST# signal also goes low before PWROK goes high, then this
is a full power failure and the reboot policy is controlled by the AFTERG3 bit.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet