82801BA Datasheet, PDF (328/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.8.3.4
9.8.3.5
PM1_TMR—Power Management 1 Timer Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 08h
(ACPI PMTMR_BLK)
xx000000h
No
Core
Attribute:
Size:
Usage:
RO
32-bit
ACPI
Bit
Description
31:24
23:0
Reserved
Timer Value (TMR_VAL)—RO. Returns the running count of the PM timer. This counter runs off a
3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to zero during a PCI reset and then
continues counting as long as the system is in the S0 state.
Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the TMROF_STS bit is
set. The High-to-Low transition will occur every 2.3435 seconds. If the TMROF_EN bit is set, an SCI
interrupt is also generated.
PROC_CNT—Processor Control Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 10h
(ACPI P_BLK)
00000000h
No (bits 7:5 are write once)
Core
Attribute:
Size:
Usage:
R/W
32-bit
ACPI or Legacy
Bit
Description
31:18 Reserved.
Throttle Status (THTL_STS)—RO.
17 ^{0 = No clock throttling is occurring (maximum processor performance).}
1 = Indicates that the clock state machine is in some type of low power state (where the processor
is not running at its maximum performance): thermal throttling or hardware throttling.
16:9 Reserved
Force Thermal Throttling (FORCE_THTL)—R/W. Software can set this bit to force the thermal
throttling function. This has the same effect as the THRM# signal being active for 2 seconds.
8 _{0 = No forced throttling.}
1 = Throttling at the duty cycle specified in THRM_DTY starts immediately (no 2 second delay), and
no SMI# is generated.
Thermal Duty Cycle (THRM_DTY). This write-once 3-bit field determines the duty cycle of the
throttling when the thermal override condition occurs. The duty cycle indicates the approximate
percentage of time the STPCLK# signal is asserted while in the throttle mode. The STPCLK# throttle
period is 1024 PCICLKs. Note that the throttling only occurs if the system is in the C0 state. If in the
C2 state, no throttling occurs.
There is no enable bit for thermal throttling, because it should not be disabled. Once the
THRM_DTY field is written, any subsequent writes will have no effect until PCIRST# goes active.
THRM_DTY Throttle Mode
PCI Clocks
7:5 ⁰⁰⁰
RESERVED (Default) 512
(Will be 50%)
001
87.5%
896
010
75.0%
768
011
62.5%
640
100
50%
512
101
37.5%
384
110
25%
256
111
12.5%
128
9-66
82801BA ICH2 and 82801BAM ICH2-M Datasheet