82801BA Datasheet, PDF (208/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
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assigned to a data stream and contains valid data. If a slot is tagged invalid with a zero in the
corresponding bit position of slot 0, the ICH2 stuffs the corresponding slot with zeros during that
slot’s active time.
Within slot 0, the first bit is a valid frame bit (slot 0, bit 15) which flags the validity of the entire
frame. If the valid frame bit is set to one, this indicates that the current frame contains at least one
slot with valid data. When there is no transaction in progress, the ICH2 deasserts the frame valid
bit. Note that after a write to slot 12, that slot always stays valid; therefore, the frame valid bit
remains set.
The next 12 bit positions of slot 0 (bits [14:3]) indicate which of the corresponding twelve time
slots contain valid data. Bits [1:0] of slot 0 are used as codec ID bits to distinguish between
separate codecs on the link.
Using the valid bits in the tag phase allows data streams of differing sample rates to be transmitted
across the link at its fixed 48 KHz frame rate. The codec can control the output sample rate of the
ICH2 using the SLOTREQ bits as described in the AC’97 specification.
Output Slot 1: Command Address Port
The command port is used to control features and monitor status of AC‘97 functions including, but
not limited to, mixer settings and power management.
The control interface architecture supports up to 64 16-bit read/write registers, addressable on even
byte boundaries. Only the even registers (00h, 02h, etc.) are valid. Output frame slot 1
communicates control register address and write/read command information.
In the case of the split codec implementation, accesses to the codecs are differentiated by the driver
using address offsets 00h–7Fh for the primary codec and address offsets 80h–FEh for the
secondary codec. The differentiation on the link, however, is done via the codec ID bits. See
Section for further details.
Output Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event that the
current command port operation is a write cycle as indicated in slot 1, bit 19. If the current
command port operation is a read then the entire slot time stuffed with 0s by the ICH2. Bits [19:4]
contain the write data. Bits [3:0] are reserved and are stuffed with zeros.
Output Slot 3: PCM Playback Left Channel
Output frame slot 3 is the composite digital audio left playback stream. Typically, this slot is
composed of standard PCM (.wav) output samples digitally mixed by the host processor. The ICH2
transmits sample streams of 16 bits and stuffs the remaining bits with zeros.
Data in output slots 3 and 4 from the ICH2 should be duplicated by software if there is only a single
channel out.
Output Slot 4: PCM Playback Right Channel
Output frame slot 4 is the composite digital audio right playback stream. Typically, this slot is
composed of standard PCM (.wav) output samples digitally mixed by the host processor. The ICH2
transmits sample streams of 16 bits and stuffs the remaining bits with zeros.
Data in output slots 3 and 4 from the ICH2 should be duplicated by software if there is only a single
channel out.
82801BA ICH2 and 82801BAM ICH2-M Datasheet