82801BA Datasheet, PDF (251/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.3
CMD—Command Register (HUB-PCI—D30:F0)
Offset Address: 04–05h
Default Value: 0001h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:10
9
8
7
6
5
4
3
2
1
0
Reserved.
Fast Back to Back Enable (FBE)—RO. Hardwired to 0. The ICH2 does not support this capability.
SERR# Enable (SERR_EN)—R/W.
1 = Enable the ICH2 to generate an NMI (or SMI# if NMI routed to SMI#) when the D30:F0 SSE bit
(offset 06h, bit 14) is set.
0 = Disable.
Wait Cycle Control—RO. Hardwired to 0
.Parity Error Response—R/W.
1 = The ICH2 is allowed to report parity errors detected on the hub interface.
0 = The ICH2 will ignore parity errors on the hub interface.
VGA Palette Snoop—RO. Hardwired to 0.
Postable Memory Write Enable (PMWE)—RO. Hardwired to 0.
Special Cycle Enable (SCE)—RO. Hardwired to 0 by P2P Bridge specification.
Bus Master Enable (BME)—R/W.
1 = Allows the Hub interface-to-PCI bridge to accept cycles from PCI to run on the hub interface.
Note: This bit does not affect the CF8h and CFCh I/O accesses.
0 = Disable
Memory Space Enable (MSE)—R/W. The ICH2 provides this bit as read/writable for software only.
However, the ICH2 ignores the programming of this bit, and runs hub interface memory cycles to
PCI.
I/O Space Enable (IOE)—R/W. The ICH2 provides this bit as read/writable for software only.
However, the ICH2 ignores the programming of this bit and runs hub interface I/O cycles to PCI that
are not intended for USB, IDE, or AC’97.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
8-3