82801BA Datasheet, PDF (103/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.7
8259 Interrupt Controllers (PIC) (D31:F0)
The ICH2 incorporates the functionality of two 8259 interrupt controllers that provide system
interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard
controller, serial ports, parallel ports, floppy disk, IDE, mouse, and DMA channels. In addition,
this interrupt controller can support the PCI-based interrupts, by mapping the PCI interrupt onto the
compatible ISA interrupt line. Each 8259 core supports 8 interrupts, numbered 0–7. Table 5-15
shows how the cores are connected.
.
Table 5-15. Interrupt Controller Core Connections
8259
Master
Slave
8259
Input
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Typical Interrupt
Source
Connected Pin / Function
Internal
Internal Timer / Counter 0 output
Keyboard
IRQ1 via SERIRQ
Internal
Slave Controller INTR output
Serial Port A
IRQ3 via SERIRQ
Serial Port B
IRQ4 via SERIRQ
Parallel Port / Generic IRQ5 via SERIRQ
Floppy Disk
IRQ6 via SERIRQ
Parallel Port / Generic IRQ7 via SERIRQ
Internal Real Time Clock Internal RTC
Generic
IRQ9 via SERIRQ
Generic
IRQ10 via SERIRQ
Generic
IRQ11 via SERIRQ
PS/2 Mouse
IRQ12 via SERIRQ
Internal
State Machine output based on processor FERR#
assertion.
Primary IDE cable IRQ14 from input signal or via SERIRQ
Secondary IDE Cable IRQ15 from input signal or via SERIRQ
The ICH2 cascades the slave controller onto the master controller through master controller
interrupt input 2. This means there are only 15 possible interrupts for the ICH2 PIC. Interrupts can
individually be programmed to be edge or level, except for IRQ[0, 2, 8#, 13].
Note that previous PIIXn devices internally latched IRQ[12 and 1] and required a port 60h read to
clear the latch. The ICH2 can be programmed to latch IRQ[12 or 1] (see bit 11 and bit 12 in
General Control Register, D31:F0, offset D0h).
82801BA ICH2 and 82801BAM ICH2-M Datasheet
5-41