82801BA Datasheet, PDF (39/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Signal Description
Table 2-5. PCI Interface Signals (Continued)
Name
Type
Description
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#
REQ[0:4]#
REQ[5]# /
REQ[B]# /
GPIO[1]
Device Select: The ICH2 asserts DEVSEL# to claim a PCI transaction. As an
output, the ICH2 asserts DEVSEL# when a PCI master peripheral attempts an
I/O
access to an internal ICH2 address or an address destined for the hub interface
(main memory or AGP). As an input, DEVSEL# indicates the response to an ICH2-
initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of
PCIRST#. DEVSEL# remains tri-stated by the ICH2 until driven by a target device.
Cycle Frame: The current Initiator drives FRAME# to indicate the beginning and
duration of a PCI transaction. While the initiator asserts FRAME#, data transfers
I/O
continue. When the initiator negates FRAME#, the transaction is in the final data
phase. FRAME# is an input to the ICH2 when the ICH2 is the target, and FRAME# is
an output from the ICH2 when the ICH2 is the Initiator. FRAME# remains tri-stated
by the ICH2 until driven by an Initiator.
Initiator Ready: IRDY# indicates the ICH2's ability, as an Initiator, to complete the
current data phase of the transaction. It is used in conjunction with TRDY#. A data
phase is completed on any clock both IRDY# and TRDY# are sampled asserted.
I/O During a write, IRDY# indicates the ICH2 has valid data present on AD[31:0]. During
a read, it indicates the ICH2 is prepared to latch data. IRDY# is an input to the ICH2
when the ICH2 is the Target and an output from the ICH2 when the ICH2 is an
Initiator. IRDY# remains tri-stated by the ICH2 until driven by an Initiator.
Target Ready: TRDY# indicates the ICH2's ability as a Target to complete the
current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A
data phase is completed when both TRDY# and IRDY# are sampled asserted.
I/O
During a read, TRDY# indicates that the ICH2, as a Target, has placed valid data on
AD[31:0]. During a write, TRDY# indicates the ICH2, as a Target is prepared to latch
data. TRDY# is an input to the ICH2 when the ICH2 is the Initiator and an output
from the ICH2 when the ICH2 is a Target. TRDY# is tri-stated from the leading edge
of PCIRST#. TRDY# remains tri-stated by the ICH2 until driven by a target.
Stop: STOP# indicates that the ICH2, as a Target, is requesting the Initiator to stop
the current transaction. STOP# causes the ICH2, as an Initiatior, to stop the current
I/O transaction. STOP# is an output when the ICH2 is a target and an input when the
ICH2 is an Initiator. STOP# is tri-stated from the leading edge of PCIRST#. STOP#
remains tri-stated until driven by the ICH2.
Calculated/Checked Parity: PAR uses "even" parity calculated on 36 bits, AD[31:0]
plus C/BE[3:0]#. "Even" parity means that the ICH2 counts the number of 1s within
the 36 bits plus PAR and the sum is always even. The ICH2 always calculates PAR
on 36 bits, regardless of the valid byte enables. The ICH2 generates PAR for
address and data phases and only guarantees PAR to be valid one PCI clock after
the corresponding address or data phase. The ICH2 drives and tri-states PAR
I/O identically to the AD[31:0] lines except that the ICH2 delays PAR by exactly one PCI
clock. PAR is an output during the address phase (delayed one clock) for all ICH2
initiated transactions. PAR is an output during the data phase (delayed one clock)
when the ICH2 is the Initiator of a PCI write transaction, and when it is the target of a
read transaction. ICH2 checks parity when it is the target of a PCI write transaction.
If a parity error is detected, the ICH2 sets the appropriate internal status bits, and
has the option to generate an NMI# or SMI#.
Parity Error: An external PCI device drives PERR# when it receives data that has a
I/O
parity error. The ICH2 drives PERR# when it detects a parity error. The ICH can
either generate an NMI# or SMI# upon detecting a parity error (either detected
internally or reported via the PERR# signal).
PCI Requests: The ICH2 supports up to 6 masters on the PCI bus. REQ[5]# is
muxed with PC/PCI REQ[B]# (must choose one or the other, but not both). If not
I ^{used for PCI or PC/PCI, REQ[5]#/REQ[B]# can instead be used as GPIO[1].}
Note: REQ[0]# is programmable to have improved arbitration latency for supporting
PCI-based 1394 controllers.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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