82801BA Datasheet, PDF (207/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
high for a total duration of 16 BIT_CLKs at the beginning of each frame. The portion of the frame
where AC_SYNC is high is defined as the tag phase. The remainder of the frame where AC_SYNC
is low is defined as the data phase. Each data bit is sampled on the falling edge of BIT_CLK.
Figure 5-22. AC-link Protocol
Tag Phase
Data Phase
20.8uS
(48 KHz)
SYNC
BIT_CLK
12.288 MHz
81.4 nS
SDIN
Codec
Ready
slot(1) slot(2)
slot(12) "0" "0" "0" 19
0
19
0 19
0
End of previous
Audio Frame
Time Slot "Valid"
Bits
("1" = time slot contains valid PCM
Slot 1
Slot 2
Slot 3
19
0
Slot 12
The ICH2 has two SDIN pins allowing a single or dual codec configuration. When two codecs are
connected, the primary and secondary codecs can be connected to either SDIN line, however it is
recommended that the primary codec be attached to SDIN [0]. The ICH2 does not distinguish
between primary and secondary codecs on its SDIN[1:0] pins; however, the registers do distinguish
between SDIN[0] and SDIN[1] for wake events, etc. The primary codec can be an AC (audio
codec), MC (modem codec), or AMC (audio/modem codec) device. The secondary codec can be
an AC, MC, or AMC device.
The MC can be either on the primary or the secondary codec, while the AC can be either on the
primary or the secondary codec, or BOTH the primary or the secondary codec.
The ICH2 does not support optional test modes as outlined in the AC’97 specification.
AC-link Output Frame (SDOUT)
A new audio output frame begins with a low to high transition of AC_SYNC. AC_SYNC is
synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of
BIT_CLK, the codec samples the assertion of AC_SYNC. This falling edge marks the time when
both sides of AC-link are aware of the start of a new frame. On the next rising edge of BIT_CLK,
the ICH2 transitions SDOUT into the first bit position of slot 0, or the valid frame bit. Each new bit
position is presented to the AC-link on a rising edge of BIT_CLK, and subsequently sampled by
the codec on the following falling edge of BIT_CLK. This sequence ensures that data transitions
and subsequent sample points for both incoming and outgoing data streams are time aligned.
The output frame data phase corresponds to the multiplexed bundles of all digital output data
targeting codec DAC inputs and control registers. Each output frame supports up to twelve
outgoing data time slots. The ICH2 generates 16 bit samples and, in compliance with the AC’97
specification, pads the 4 least significant bits of valid slots with zeros.
The output data stream is sent with the most significant bit first and all invalid slots are stuffed with
0s. When mono audio sample streams are output from the ICH2, software must ensure both left and
right sample stream time slots are filled with the same data.
Output Slot 0: Tag Phase
Slot 0 is considered the tag phase. The tag phase is a special 16 bit time slot wherein each bit
conveys a valid tag for its corresponding time slot within the current frame. A one in a given bit
position of slot 0 indicates that the corresponding time slot within the current frame has been
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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