82801BA Datasheet, PDF (154/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
PWROK Signal
The PWROK input should go active based on the core supply voltages becoming valid. PWROK
should go active no sooner than 10 ms after Vcc3_3 and VCC1_8 have reached their nominal
values.
Note:
Traditional designs have a reset button logically AND’d with the PWROK signal from the power
supply and the processor’s voltage regulator module. If this is done with the ICH2, the
PWROK_FLR bit will be set. The ICH2 treats this internally as if the RSMRST# signal had gone
active. However, it is not treated as a full power failure. If PWROK goes inactive and then active
(but RSMRST# stays high), the ICH2 reboots (regardless of the state of the AFTERG3 bit). If the
RSMRST# signal also goes low before PWROK goes high, this is a full power failure and the
reboot policy is controlled by the AFTERG3 bit.
VRMPWRGD Signal
This signal is connected to the processor’s VRM and is internally AND’d with the PWROK signal
that comes from the system power supply. This is needed for Intel^® SpeedStep^TM technology
support in mobile systems (ICH2-M 82801BAM) and saves the external AND gate found in
desktop systems (82801BA ICH2).
BATLOW#—Battery Low (82801BAM ICH2-M)
For the ICH2-M, the BATLOW# input can inhibit waking from a sleep state if there is not
sufficient power. It will also cause an SMI#, if the system is already in an S0 state.
Controlling Leakage and Power Consumption During Low-Power States
To control leakage in the system, various signals will tri-state or go low during some low-power
states.
General principles
• All signals going to powered down planes (either internally or externally) must be either tri-
stated or driven low.
• Signals with pull-up resistors should not be low during low-power states. This is to avoid the
power consumed in the pull-up resistor.
• Buses should be halted (and held) in a known state to avoid a floating input (perhaps to some
other device). Floating inputs can cause extra power consumption.
Based on the above principles, the following measures are taken:
• During C2 or S3 state (C2, S3, or C3 state for ICH2-M), the processor signals that have pull-
ups will be tri-stated or driven low.
• During S3 (STR), all signals attached to powered down planes will be tri-stated or driven low.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet