82801BA Datasheet, PDF (487/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

I/O Register Index
Table A-2. ICH2 Variable I/O Registers (Continued)
Register Name
Offset
EDS Section and Location
Block Data Byte
Receive Slave Address
Receive Slave Data
07h
Section 12.2.7, “BLOCK_DB—Block Data Byte
Register” on page 12-10
09h
Section 12.2.8, “RCV_SLVA—Receive Slave Address
Register” on page 12-10
0Ah
Section 12.2.9, “SLV_DATA—Receive Slave Data
Register” on page 12-10
AC’97 Audio I/O Registers at NAMBAR + Offset
NAMBAR is set at Section 13.1.11, “NABMBAR—Native Audio Bus Mastering Base Address Register
(Audio—D31:F5)” on page 13-5
PCM In Buffer Descriptor list Base
Address Register
PCM In Current Index Value
PCM In Last Valid Index
PCM In Status Register
PCM In Position In Current Buffer
PCM In Prefetched Index Value
PCM In Control Register
PCM Out Buffer Descriptor list Base
Address Register
PCM Out Current Index Value
PCM Out Last Valid Index
PCM Out Status Register
PCM Out Position In Current Buffer
PCM Out Prefetched Index Value
PCM Out Control Register
Mic. In Buffer Descriptor list Base
Address Register
Mic. In Current Index Value
Mic. In Last Valid Index
Mic. In Status Register
Mic In Position In Current Buffer
Mic. In Prefetched Index Value
Mic. In Control Register
00h
Section 13.2.1, “x_BDBAR—Buffer Descriptor Base
Address Register” on page 13-9
04h
Section 13.2.2, “x_CIV—Current Index Value
Register” on page 13-10
05h
Section 13.2.3, “x_LVI—Last Valid Index Register” on
page 13-10
06h
Section 13.2.4, “x_SR—Status Register” on
page 13-11
08h
Section 13.2.5, “x_PICB—Position In Current Buffer
Register” on page 13-12
0Ah
Section 13.2.6, “x_PIV—Prefetched Index Value
Register” on page 13-12
0Bh
Section 13.2.7, “x_CR—Control Register” on
page 13-13
10h
Section 13.2.1, “x_BDBAR—Buffer Descriptor Base
Address Register” on page 13-9
14h
Section 13.2.2, “x_CIV—Current Index Value
Register” on page 13-10
15h
Section 13.2.3, “x_LVI—Last Valid Index Register” on
page 13-10
16h
Section 13.2.4, “x_SR—Status Register” on
page 13-11
18h
Section 13.2.5, “x_PICB—Position In Current Buffer
Register” on page 13-12
1Ah
Section 13.2.6, “x_PIV—Prefetched Index Value
Register” on page 13-12
1Bh
Section 13.2.7, “x_CR—Control Register” on
page 13-13
20h
Section 13.2.1, “x_BDBAR—Buffer Descriptor Base
Address Register” on page 13-9
24h
Section 13.2.2, “x_CIV—Current Index Value
Register” on page 13-10
25h
Section 13.2.3, “x_LVI—Last Valid Index Register” on
page 13-10
26h
Section 13.2.4, “x_SR—Status Register” on
page 13-11
28h
Section 13.2.5, “x_PICB—Position In Current Buffer
Register” on page 13-12
2Ah
Section 13.2.6, “x_PIV—Prefetched Index Value
Register” on page 13-12
2Bh
Section 13.2.7, “x_CR—Control Register” on
page 13-13
82801BA ICH2 and 82801BAM ICH2-M Datasheet
A-9