82801BA Datasheet, PDF (363/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

IDE Controller Registers (D31:F1)
Bit
Description
Primary Drive 1 Cycle Time (PCT1)—R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
PCB1 = 0 (33 MHz clk)
PCB1 = 1 (66 MHz clk)
5:4 _{00 = CT 4 clocks, RP 6 clocks 00 = Reserved}
FAST_PCB1 = 1 (133 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clks, RP 16 clks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
3:2 Reserved.
Primary Drive 0 Cycle Time (PCT0)—R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
PCB1 = 0 (33 MHz clk)
PCB1 = 1 (66 MHz clk)
1:0 _{00 = CT 4 clocks, RP 6 clocks 00 = Reserved}
FAST_PCB1 = 1 (133 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clks, RP 16 clks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
10.1.17
IDE_CONFIG—IDE I/O Configuration Register
Address Offset: 54h
Default Value: 00h
Attribute:
Size:
R/W
32 bits
Bit
31:20
19:18
17:16
15
Description
Reserved.
Secondary IDE Signal Mode (SEC_SIG_MODE)—R/W.
00 = Normal (Enabled).
01 = Tri-state (Disabled).
10 = Drive low (Disabled).
11 = Reserved.
ICH2 (82801BA):
These bits are used to control mode of the Secondary IDE signal pins. These bits should always be
set to 00b for desktop implementations.
ICH2-M (82801BAM):
These bits are used to control mode of the Secondary IDE signal pins for mobile swap bay support.
Primary IDE Signal Mode (PRIM_SIG_MODE)—R/W.
00 = Normal (Enabled).
01 = Tri-state (Disabled).
10 = Drive low (Disabled).
11 = Reserved.
ICH2 (82801BA):
These bits are used to control mode of the Primary IDE signal pins. These bits should always be
set to 00b for desktop implementations.
ICH2-M (82801BAM):
These bits are used to control mode of the Secondary IDE signal pins for mobile swap bay support.
Fast Secondary Drive 1 Base Clock (FAST_SCB1)—R/W. This bit is used in conjuction with the
SCT1 bits to enable/disable Ultra ATA/100 timings for the Secondary Slave drive.
0 = Disable Ultra ATA/100 timing for the Secondary Slave drive.
1 = Enable Ultra ATA/100 timing for the Secondary Slave drive (overrides bit 3 in this register).
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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