82801BA Datasheet, PDF (482/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

I/O Register Index
Table A-1. ICH2 Fixed I/O Registers (Continued)
Register Name
Advanced Power Management
Control Port Register
Advanced Power Management
Status Port Register
Aliased at A0h–A1h
Aliased at A0h–A1h
Aliased at A0h–A1h
Channel 4 DMA Base & Current
Address Register
Aliased at C0h
Channel 4 DMA Base & Current
Count Register
Aliased at C2h
Channel 5 DMA Base & Current
Address Register
Aliased at C4h
Channel 5 DMA Base & Current
Count Register
Aliased at C6h
Channel 6 DMA Base & Current
Address Register
Aliased at C8h
Channel 6 DMA Base & Current
Count Register
Aliased at CAh
Channel 7 DMA Base & Current
Address Register
Aliased at CCh
Channel 7 DMA Base & Current
Count Register
Aliased at CEh
Channel 4–7 DMA Command
Register
Channel 4–7 DMA Status Register
Aliased at D0h
Channel 4–7 DMA Write Single
Mask Register
Aliased at D4h
Channel 4–7 DMA Channel Mode
Register
Aliased at D6h
Channel 4–7 DMA Clear Byte
Pointer Register
Aliased at D8h
Port
B2h
B3h
B4h–B5h
B8h–B9h
BCh–BDh
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D4h
D5h
D6h
D7h
D8h
D9h
EDS Section and Location
Section 9.8.2.1, “APM_CNT—Advanced Power
Management Control Port Register” on page 9-60
Section 9.8.2.2, “APM_STS—Advanced Power
Management Status Port Register” on page 9-60
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-24
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-25
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-24
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-25
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-24
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-25
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-24
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-25
Section 9.2.4, “DMACMD—DMA Command Register”
on page 9-26
Section 9.2.5, “DMASTS—DMA Status Register” on
page 9-26
Section 9.2.6, “DMA_WRSMSK—DMA Write Single
Mask Register” on page 9-27
Section 9.2.7, “DMACH_MODE—DMA Channel Mode
Register” on page 9-27
Section 9.2.8, “DMA Clear Byte Pointer Register” on
page 9-28
A-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet