82801BA Datasheet, PDF (218/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Write Cycles (Single Byte)
All devices that support FWH memory write cycles must support single byte writes. FWH memory
write cycles use the same preamble as FWH memory read cycles that is described above.
Figure 5-27. Single Byte Write
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CLK
FRAME#
AD[3:0]
Preamble
D_Lo D_Hi
TAR
SYNC
TAR
Figure 5-27 shows an FWH memory write cycle where a single byte is transferred. The master
asserts an MSIZE value of 0. After the address has been transferred, the 2 clock data phase begins.
Following the data phase, bus ownership is transferred to the FWH component with a TAR cycle.
Following the TAR phase, the device must assert a SYNC value of ‘0000b’ (ready) or ‘1010b’
(error) indicating the data has been received. Bus ownership is then given back to the master with
another TAR phase.
FWH Memory Writes only allow one clock for the SYNC phase. The TAR + SYNC + TAR phases
at the end of FWH memory write cycles must be exactly 5 clocks.
Error Reporting
There is no error reporting over the FWH interface for FWH memory cycles. If an error occurs
(e.g., an address out of range or an unsupported memory size), the cycle will continue from the host
unabated. This is because these errors are the result of illegal programming, and there is no
efficient error reporting method that can be done to counter the programming error.
Therefore, the FWH component must not report the error conditions over the FWH interface. It
must only report wait states and the ‘ready’ condition. It may choose to log the error internally to
be debugged, but it must not signal an error through the FWH interface itself
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82801BA ICH2 and 82801BAM ICH2-M Datasheet