82801BA Datasheet, PDF (191/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Table 5-75. USB Legacy Keyboard State Transitions
Current State Action Data Value Next State
Comment
IDLE
IDLE
IDLE
IDLE
IDLE
GateState1
GateState1
GateState1
GateState1
GateState1
GateState2
GateState2
GateState2
GateState2
GateState2
64h / Write
64h / Write
64h / Read
60h / Write
60h / Read
60h / Write
64h / Write
64h / Write
60h / Read
64h / Read
64 / Write
64h / Write
64h / Read
60h / Write
60h / Read
D1h
GateState1
Standard D1 command. Cycle passed through to
8042. SMI# doesn't go active. PSTATE goes to 1.
Not D1h
IDLE
Bit 3 in configuration Register determines if cycle
passed through to 8042 and if SMI# generated.
N/A
IDLE
Bit 2 in configuration Register determines if cycle
passed through to 8042 and if SMI# generated.
Don't Care
IDLE
Bit 1 in configuration Register determines if cycle
passed through to 8042 and if SMI# generated.
N/A
IDLE
Bit 0 in configuration Register determines if cycle
passed through to 8042 and if SMI# generated.
Cycle passed through to 8042, even if trap
enabled in Bit 1 in configuration Register. No
XXh
GateState2 SMI# generated. PSTATE remains 1. If data
value is not DFh or DDh then the 8042 may
chose to ignore it.
Cycle passed through to 8042, even if trap
enabled via Bit 3 in configuration Register. No
D1h
GateState1 SMI# generated. PSTATE remains 1. Stay in
GateState1 because this is part of the double-
trigger sequence.
Not D1h
ILDE
Bit 3 in configuration space determines if cycle
passed through to 8042 and if SMI# generated.
PSTATE goes to 0. If Bit 7 in configuration
Register is set, then SMI# should be generated.
This is an invalid sequence. Bit 0 in configuration
Register determines if cycle passed through to
N/A
IDLE 8042 and if SMI# generated. PSTATE goes to 0.
If Bit 7 in configuration Register is set, then SMI#
should be generated.
Just stay in same state. Generate an SMI# if
N/A
GateState1 enabled in Bit 2 of configuration Register.
PSTATE remains 1.
Standard end of sequence. Cycle passed through
FFh
IDLE to 8042. PSTATE goes to 0. Bit 7 in configuration
Space determines if SMI# should be generated.
Not FFh
IDLE
Improper end of sequence. Bit 3 in configuration
Register determines if cycle passed through to
8042 and if SMI# generated. PSTATE goes to 0.
If Bit 7 in configuration Register is set, then SMI#
should be generated.
Just stay in same state. Generate an SMI# if
N/A
GateState2 enabled in Bit 2 of configuration Register.
PSTATE remains 1.
Improper end of sequence. Bit 1 in configuration
Register determines if cycle passed through to
XXh
IDLE 8042 and if SMI# generated. PSTATE goes to 0.
If Bit 7 in configuration Register is set, then SMI#
should be generated.
Improper end of sequence. Bit 0 in configuration
Register determines if cycle passed through to
N/A
IDLE 8042 and if SMI# generated. PSTATE goes to 0.
If Bit 7 in configuration Register is set, then SMI#
should be generated.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
5-129