82801BA Datasheet, PDF (364/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

IDE Controller Registers (D31:F1)
Bit
Description
Fast Secondary Drive 0 Base Clock (FAST_SCB0)—R/W. This bit is used in conjuction with the
SCT0 bits to enable/disable Ultra ATA/100 timings for the Secondary Master drive.
14
0 = Disable Ultra ATA/100 timing for the Secondary Master drive.
1 = Enable Ultra ATA/100 timing for the Secondary Master drive (overrides bit 2 in this register).
Fast Primary Drive 1 Base Clock (FAST_PCB1)—R/W. This bit is used in conjuction with the
PCT1 bits to enable/disable Ultra ATA/100 timings for the Primary Slave drive.
13
0 = Disable Ultra ATA/100 timing for the Primary Slave drive.
1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this register).
Fast Primary Drive 0 Base Clock (FAST_PCB0)—R/W. This bit is used in conjuction with the
PCT0 bits to enable/disable Ultra ATA/100 timings for the Primary Master drive.
12
0 = Disable Ultra ATA/100 timing for the Primary Master drive.
1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this register).
11 Reserved.
Write Buffer PingPong Enable (WR_PingPong_EN)—R/W.
10 _{0 = Disabled. The buffer will behave similar to PIIX4.}
1 = Enables the write buffer to be used in a split (ping/pong) manner.
9:8 Reserved.
Secondary Slave Channel Cable Reporting—R/W. BIOS should program this bit to tell the IDE
driver which cable is plugged into the channel.
7
0 = 40 conductor cable is present.
1 = 80 conductor cable is present.
6
Secondary Master Channel Cable Reporting—R/W. Same description as bit 7
5
Primary Slave Channel Cable Reporting—R/W. Same description as bit 7
4
Primary Master Channel Cable Reporting—R/W. Same description as bit 7
Secondary Drive 1 Base Clock (SCB1)—R/W.
3
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
Secondary Drive 0 Base Clock (SCBO)—R/W.
2
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
Primary Drive 1 Base Clock (PCB1)—R/W.
1
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
Primary Drive 0 Base Clock (PCB0)—R/W.
0
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
10-10
82801BA ICH2 and 82801BAM ICH2-M Datasheet