82801BA Datasheet, PDF (233/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LAN Controller Registers (B1:D8:F0)
7.1.16
7.1.17
7.1.18
7.1.19
INT_LN—Interrupt Line Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0
Interrupt Line (INT_LN)—R/W. Identifies the system interrupt line to which the LAN Controller’s
PCI interrupt request pin (as defined in the Interrupt Pin Register) is routed.
INT_PN—Interrupt Pin Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Dh
Default Value: 01h
Attribute:
Size:
RO
8 bits
Bit
Description
Interrupt Pin (INT_PN)—RO. Hardwired to 01h to indicate that the LAN Controller’s interrupt
7:0 request is connected to PIRQA#. However, in the ICH2 implementation, when the LAN Controller
interrupt is generated PIRQ[E]# will go active, not PIRQ[A]#.
MIN_GNT—Minimum Grant Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Eh
Default Value: 08h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Minimum Grant (MIN_GNT)—RO. Indicates the amount of time (in increments of 0.25 µs) that the
LAN Controller needs to retain ownership of the PCI bus when it initiates a transaction.
MAX_LAT—Maximum Latency Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Fh
Default Value: 38h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Maximum Latency (MAX_LAT)—RO. Defines how often (in increments of 0.25 µs) the LAN
Controller needs to access the PCI bus.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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