82801BA Datasheet, PDF (483/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

I/O Register Index
Table A-1. ICH2 Fixed I/O Registers (Continued)
Register Name
Channel 4–7 DMA Master Clear
Register
Aliased at DAh
Channel 4–7 DMA Clear Mask
Register
Aliased at DCh
Channel 4–7 DMA Write All Mask
Register
Aliased at DEh
Coprocessor Error Reigster
PIO Mode Command Block Offset
for Secondary Drive
PIO Mode Command Block Offset
for Primary Drive
PIO Mode Control Block Offset for
Secondary Drive
PIO Mode Control Block Offset for
Primary Drive
Master PIC Edge/Level Triggered
Register
Slave PIC Edge/Level Triggered
Register
Reset Control Register
Port
DAh
DBh
DCh
DEh
DEh
DFh
F0h
EDS Section and Location
Section 9.2.9, “DMA Master Clear Register” on
page 9-28
Section 9.2.10, “DMA_CLMSK—DMA Clear Mask
Register” on page 9-28
Section 9.2.11, “DMA_WRMSK—DMA Write All Mask
Register” on page 9-29
Section 9.7.4, “COPROC_ERR—Coprocessor Error
Register” on page 9-52
170h–177h See ATA Specification for detailed register description
1F0h–1F7h See ATA Specification for detailed register description
376h
See ATA Specification for detailed register description
3F6h
4D0h
4D1h
CF9h
See ATA Specification for detailed register description
Section 9.4.10, “ELCR1—Master Controller Edge/Level
Triggered Register” on page 9-39
Section 9.4.11, “ELCR2—Slave Controller Edge/Level
Triggered Register” on page 9-40
Section 9.7.5, “RST_CNT—Reset Control Register” on
page 9-53
NOTE: When the POS_DEC_EN bit is set, additional I/O ports get positively decoded by the ICH2. Refer to
through for a listing of these ranges.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
A-5