82801BA Datasheet, PDF (408/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

AC’97 Audio Controller Registers (D31:F5)
13.2.8
GLOB_CNT—Global Control Register
I/O Address:
Default Value:
Lockable:
NABMBAR + 2Ch
00000000h
No
Attribute:
Size:
Power Well:
This register can be accessed only as a DWord (32 bits).
R/W (DWord access only)
32 bits
Core
Bit
31:22
21:20
19:6
5
4
3
2
1
0
Description
Reserved.
PCM 4/6 Enable—R/W. Configures PCM Output for 2, 4 or 6 channel mode.
00 = 2-channel mode (default)
01 = 4-channel mode
10 = 6-channel mode
11 = Reserved
Reserved.
Secondary Resume Interrupt Enable—R/W.
0 = Disable.
1 = Enable an interrupt to occur when the secondary codec causes a resume event on the
AC-link.
Primary Resume Interrupt Enable—R/W.
0 = Disable.
1 = Enable an interrupt to occur when the primary codec causes a resume event on the AC-link.
ACLINK Shut Off—R/W.
0 = Normal operation.
1 = Drive all AC’97 outputs low and turn off all AC’97 input buffer enables
AC’97 Warm Reset—R/W (special).
0 = Normal operation.
1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset will awaken
a suspended codec without clearing its internal registers. If software attempts to perform a
warm reset while bit_clk is running, the write will be ignored and the bit will not change. This bit
is self-clearing (it remains set until the reset completes and bit_clk is seen on the ACLink, after
which it clears itself).
AC ‘97 Cold Reset#—R/W.
0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC ‘97 circuitry. All data in
the controller and the codec will be lost. Software needs to clear this bit no sooner than the
minimum number of ms have elapsed.
1 = This bit defaults to 0; thus, after reset, the driver needs to set this bit to a 1. The value of this
bit is retained after suspends; thus, if this bit is set to a 1 prior to suspending, a cold reset is not
generated automatically upon resuming.
Note: This bit is in the Resume well, not in the Core well.
GPI Interrupt Enable (GIE)—R/W. This bit controls whether the change in status of any GPI
causes an interrupt.
0 = Bit 0 of the Global Status Register is set, but no interrupt is generated.
1 = The change on value of a GPI causes an interrupt and sets bit 0 of the Global Status Register.
13-14
82801BA ICH2 and 82801BAM ICH2-M Datasheet