82801BA Datasheet, PDF (421/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

AC’97 Modem Controller Registers (D31:F6)
14.2.5
14.2.6
14.2.7
x_PICB—Position In Current Buffer Register
I/O Address:
Default Value:
Lockable:
MBAR + 08h (MIPICB),
MBAR + 18h (MOPICB),
0000h
No
Attribute:
Size:
Power Well:
This register can be accessed only as a Word (16 bits).
RO (Word access only)
16 bits
Core
Bit
Description
15:0
Position In Current Buffer[15:0]—RO. These bits represent the number of DWords left to be
processed in the current buffer.
x_PIV—Prefetch Index Value Register
I/O Address:
Default Value:
Lockable:
MBAR + 0Ah (MIPIV),
MBAR + 1Ah (MOPIV)
00h
No
Attribute:
Size:
Power Well:
RO
8 bits
Core
Bit
Description
7:5 Hardwired to 0
4:0
Prefetched Index value [4:0]—RO. These bits represent which buffer descriptor in the list has
been prefetched.
x_CR—Control Register
I/O Address:
Default Value:
Lockable:
MBAR + 0Bh (MICR),
MBAR + 1Bh (MOCR)
00h
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
Bit
Description
7:5 Reserved.
Interrupt On Completion Enable (IOCE)—R/W. This bit controls whether or not an interrupt
occurs when a buffer completes with the IOC bit set in its descriptor.
4
0 = Disable.
1 = Enable.
FIFO Error Interrupt Enable (FEIE)—R/W. This bit controls whether the occurrence of a FIFO
error will cause an interrupt or not.
3
0 = Disable. Bit 4 in the Status Register will be set, but the interrupt will not occur.
1 = Enable. Interrupt will occur
Last Valid Buffer Interrupt Enable (LVBIE)—R/W. This bit controls whether the completion of the
last valid buffer will cause an interrupt or not.
2
0 = Disable. Bit 2 in the Status register will still be set, but the interrupt will not occur.
1 = Enable.
Reset Registers (RR)—R/W (special).
1 = Contents of all registers to be reset, except the interrupt enable bits (bit 4,3,2 of this register).
Software needs to set this bit. It must be set only when the Run/Pause bit is cleared. Setting it
1
when the Run bit is set will cause undefined consequences. This bit is self-clearing (software
does not need to clear it).
0 = Removes reset condition.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
14-11