82801BA Datasheet, PDF (152/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Table 5-48. Write Only Registers with Read Paths in Alternate Access Mode (Continued)
Restore Data
Restore Data
I/O
Addr
# of
Rds
Access
Data
I/O
Addr
# of
Rds
Access
Data
1
DMA Chan 0–3
Command²
CAh 2
2
DMA Chan 0–3 Request
1
DMA Chan 6 base count low
byte
2
DMA Chan 6 base count high
byte
08h 6
3
DMA Chan 0 Mode:
Bits(1:0) = “00”
4
DMA Chan 1 Mode:
Bits(1:0) = “01”
CCh 2
1
DMA Chan 7 base address low
byte
2
DMA Chan 7 base address high
byte
5
DMA Chan 2 Mode:
Bits(1:0) = “10”
6
DMA Chan 3 Mode:
Bits(1:0) = “11”.
CEh 2
1
DMA Chan 7 base count low
byte
2
DMA Chan 7 base count high
byte
1
PIC ICW2 of Master
controller
1
DMA Chan 4–7 Command²
2
PIC ICW3 of Master
controller
2
DMA Chan 4–7 Request
3
PIC ICW4 of Master
controller
4
PIC OCW1 of Master
controller¹
D0h 6
3
DMA Chan 4 Mode:
Bits(1:0) = “00”
4
DMA Chan 5 Mode:
Bits(1:0) = “01”
5
PIC OCW2 of Master
controller
5
DMA Chan 6 Mode:
Bits(1:0) = “10”
20h 12
6
PIC OCW3 of Master
controller
7
PIC ICW2 of Slave
controller
6
DMA Chan 7 Mode:
Bits(1:0) = “11”.
8
PIC ICW3 of Slave
controller
9
PIC ICW4 of Slave
controller
10
PIC OCW1 of Slave
controller¹
11
PIC OCW2 of Slave
controller
12
PIC OCW3 of Slave
controller
NOTE:
1. The OCW1 register must be read before entering Alternate Access Mode.
2. Bits 5, 3, 1, and 0 return 0.
5-90
82801BA ICH2 and 82801BAM ICH2-M Datasheet