82801BA Datasheet, PDF (304/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.5.3
DAT—Data Register
Memory Address FEC0_0010h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
This is a 32 bit register specifying the data to be read or written to the register pointed to by the
Index register. This register can only be accessed in DWord quantities.
Bit
Description
7:0
APIC Data—R/W. This is a 32 bit register for the data to be read or written to the APIC indirect
register pointed to by the Index register.
9.5.4 IRQPA—IRQ Pin Assertion Register
Memory Address FEC0_0020h
Default Value: N/A
Attribute:
Size:
WO
32 bits
The IRQ Pin Assertion Register is present to provide a mechanism to scale the number of interrupt
inputs into the I/O APIC without increasing the number of dedicated input pins. When a device that
supports this interrupt assertion protocol requires interrupt service, that device will issue a write to
this register. Bits 4:0 written to this register contain the IRQ number for this interrupt. The only
valid values are 0–23. Bits 31:5 are ignored. To provide for future expansion, peripherals should
always write a value of 0 for Bits 31:5.
See Section 5.8.4 for more details on how PCI devices will use this field.
Note: Writes to this register are only allowed by the processor and by masters on the ICH2’s PCI bus.
Writes by devices on PCI buses above the ICH2 (e.g., a PCI segment on a P64H) are not supported.
Bit
31:5
4:0
Description
Reserved. Bits 31:5 are ignored.
IRQ Number—WO. Bits 4:0 written to this register contain the IRQ number for this interrupt. The
only valid values are 0–23.
9-42
82801BA ICH2 and 82801BAM ICH2-M Datasheet