82801BA Datasheet, PDF (8/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

5.5.8 Asserting DMA Requests...............................................................5-33
5.5.9 Abandoning DMA Requests ..........................................................5-34
5.5.10 General Flow of DMA Transfers ....................................................5-35
5.5.11 Terminal Count ..............................................................................5-35
5.5.12 Verify Mode....................................................................................5-35
5.5.13 DMA Request Deassertion ............................................................5-36
5.5.14 SYNC Field / LDRQ# Rules ...........................................................5-37
5.6 8254 Timers (D31:F0).................................................................................5-38
5.6.1 Timer Programming .......................................................................5-38
5.6.2 Reading from the Interval Timer ....................................................5-39
5.7 8259 Interrupt Controllers (PIC) (D31:F0) ..................................................5-41
5.7.1 Interrupt Handling ..........................................................................5-42
5.7.1.1 Generating Interrupts .....................................................5-42
5.7.1.2 Acknowledging Interrupts ...............................................5-42
5.7.1.3 Hardware/Software Interrupt Sequence .........................5-43
5.7.2 Initialization Command Words (ICWx) ...........................................5-43
5.7.3 Operation Command Words (OCW) ..............................................5-44
5.7.4 Modes of Operation .......................................................................5-45
5.7.5 Masking Interrupts .........................................................................5-47
5.7.6 Steering PCI Interrupts ..................................................................5-47
5.8 Advanced Interrupt Controller (APIC) (D31:F0) ..........................................5-48
5.8.1 Interrupt Handling ..........................................................................5-48
5.8.2 Interrupt Mapping...........................................................................5-49
5.8.3 APIC Bus Functional Description...................................................5-50
5.8.3.1 Physical Characteristics of APIC....................................5-50
5.8.3.2 APIC Bus Arbitration ......................................................5-50
5.8.3.3 Bus Message Formats ...................................................5-51
5.8.4 PCI Message-Based Interrupts......................................................5-56
5.8.4.1 Theory of Operation .......................................................5-56
5.8.4.2 Registers and Bits Associated with PCI Interrupt
Delivery ..........................................................................5-56
5.8.5 Front-Side Interrupt Delivery..........................................................5-57
5.8.5.1 Theory of Operation .......................................................5-57
5.8.5.2 Edge-Triggered Operation..............................................5-57
5.8.5.3 Level-Triggered Operation .............................................5-57
5.8.5.4 Registers Associated with Front-Side Bus Interrupt
Delivery ..........................................................................5-58
5.8.5.5 Interrupt Message Format ..............................................5-58
5.9 Serial Interrupt (D31:F0) .............................................................................5-60
5.9.1 Start Frame....................................................................................5-60
5.9.2 Data Frames ..................................................................................5-60
5.9.3 Stop Frame ....................................................................................5-61
5.9.4 Specific Interrupts not Supported via SERIRQ ..............................5-61
5.9.5 Data Frame Format .......................................................................5-62
5.10 Real Time Clock (D31:F0) ..........................................................................5-63
5.10.1 Update Cycles ...............................................................................5-63
5.10.2 Interrupts........................................................................................5-64
5.10.3 Lockable RAM Ranges ..................................................................5-64
5.10.4 Century Rollover ............................................................................5-64
5.10.5 Clearing Battery-Backed RTC RAM...............................................5-64
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82801BA ICH2 and 82801BAM ICH2-M Datasheet